gicv3: a3700: save and restore SPI and PPI state during low power mode

The SPI and PPI irq states are saved during core power off or suspend,
and resumed during core up or resume.

Change-Id: Ib41a28b453d07cc718c61ab2246dfa382c2d87bf
Signed-off-by: Victor Gu <xigu@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/37432
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Hua Jing <jinghua@marvell.com>
Signed-off-by: zachary <zhangzg@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38078
Tested-by: Hua Jing <jinghua@marvell.com>
Signed-off-by: zachary <zhangzg@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38610

2 files changed, 22 insertions, 0 deletions

diff --git a/plat/marvell/a3700/common/a3700_common.mk b/plat/marvell/a3700/common/a3700_common.mk
index 4d658fe8..b3a6b5ce 100644
--- a/plat/marvell/a3700/common/a3700_common.mk
+++ b/plat/marvell/a3700/common/a3700_common.mk
@@ -56,6 +56,7 @@ PLAT_INCLUDES		:=	-I$(PLAT_FAMILY_BASE)/$(PLAT)			\
 				-I$(PLAT_COMMON_BASE)/include			\
 				-I$(PLAT_INCLUDE_BASE)/common			\
 				-I$(MARVELL_DRV_BASE)/uart			\
+				-I$/drivers/arm/gic/common/			\
 				$(ATF_INCLUDES)
 
 PLAT_BL_COMMON_SOURCES	:=	$(PLAT_COMMON_BASE)/aarch64/a3700_common.c	\
diff --git a/plat/marvell/a3700/common/plat_pm.c b/plat/marvell/a3700/common/plat_pm.c
index 04aaffaf..4d357390 100644
--- a/plat/marvell/a3700/common/plat_pm.c
+++ b/plat/marvell/a3700/common/plat_pm.c
@@ -286,6 +286,9 @@ void a3700_pwr_domain_off(const psci_power_state_t *target_state)
 {
 	uint32_t cpu_idx = plat_my_core_pos();
 
+	/* Save the per-cpu IRQ state */
+	plat_marvell_gic_irq_pcpu_save();
+
 	/* Disable the GIC CPU interface */
 	plat_marvell_gic_cpuif_disable();
 
@@ -574,12 +577,22 @@ static void a3700_pm_clear_lp_flag(void)
 	mmio_clrbits_32(MVEBU_PM_CPU_VDD_OFF_INFO_2_REG, MVEBU_PM_LOW_POWER_STATE);
 }
 
+static uint32_t a3700_pm_get_lp_flag(void)
+{
+	/* Get the flag for enter the low power mode */
+	return mmio_read_32(MVEBU_PM_CPU_VDD_OFF_INFO_2_REG) & MVEBU_PM_LOW_POWER_STATE;
+}
+
 /*******************************************************************************
  * A3700 handler called when a power domain is about to be suspended. The
  * target_state encodes the power state that each level should transition to.
  ******************************************************************************/
 void a3700_pwr_domain_suspend(const psci_power_state_t *target_state)
 {
+	/* Save IRQ states */
+	plat_marvell_gic_irq_save();
+	plat_marvell_gic_irq_pcpu_save();
+
 	/* Prevent interrupts from spuriously waking up this cpu */
 	plat_marvell_gic_cpuif_disable();
 
@@ -614,6 +627,10 @@ void a3700_pwr_domain_on_finish(const psci_power_state_t *target_state)
 	/* Per-CPU interrupt initialization */
 	plat_marvell_gic_pcpu_init();
 	plat_marvell_gic_cpuif_enable();
+
+	/* Restore the per-cpu IRQ state */
+	if (a3700_pm_get_lp_flag())
+		plat_marvell_gic_irq_pcpu_restore();
 }
 
 /*******************************************************************************
@@ -635,6 +652,10 @@ void a3700_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
 	/* Interrupt initialization */
 	plat_marvell_gic_init();
 
+	/* Restore IRQ states */
+	plat_marvell_gic_irq_restore();
+	plat_marvell_gic_irq_pcpu_restore();
+
 	/*
 	 * Initialize CCI for this cluster after resume from suspend state.
 	 * No need for locks as no other CPU is active.