diff options
| author | Igal Liberman <igall@marvell.com> | 2017-06-13 14:01:58 +0300 |
|---|---|---|
| committer | Kostya Porotchkin <kostap@marvell.com> | 2017-06-27 18:33:03 +0300 |
| commit | 51b7b447188428f25921d6b7977bb5177748f2cb (patch) | |
| tree | a1fea463bdd446319666229fe5c64eaee5a7f69e | |
| parent | 609cd80091408f474b81116432c5c323cb06ae79 (diff) | |
Revert "fix: pcie: temporarily disable pcie clock fix"
This reverts commit 3cf300e7695e6883787ce01d5c4b97ced96bb8c1.
Following u-boot 2017 fix, we can use the correct setting for
PCIe clock direction.
Change-Id: If65ffad0bb507392d7815d00ef6dff62d5ccb9dc
Reviewed-on: http://vgitil04.il.marvell.com:8080/40780
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
| -rw-r--r-- | drivers/marvell/mochi/cp110_setup.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/drivers/marvell/mochi/cp110_setup.c b/drivers/marvell/mochi/cp110_setup.c index fcbd16ae..579dc9f7 100644 --- a/drivers/marvell/mochi/cp110_setup.c +++ b/drivers/marvell/mochi/cp110_setup.c @@ -310,12 +310,6 @@ void cp110_pcie_clk_cfg(int cp_index) mmio_write_32(MVEBU_PCIE_REF_CLK_BUF_CTRL(cp_index), reg); } -#if 0 - /* - * TODO: Some instabilities in PCIe occur after introducing this code. - * Until we understand the root cause of this issue, - * disable it temporarily. - */ /* CP110 revision A1 */ if (cp110_rev_id_get() == MVEBU_CP110_REF_ID_A1) { if (!pcie0_clk || !pcie1_clk) { @@ -329,7 +323,6 @@ void cp110_pcie_clk_cfg(int cp_index) mmio_write_32(MVEBU_CP_MSS_DPSHSR_REG(cp_index), reg); } } -#endif } /* Set a unique stream id for all DMA capable devices */ |