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authorTerry Zhou <bjzhou@marvell.com>2018-04-28 10:53:38 +0800
committerKostya Porotchkin <kostap@marvell.com>2018-06-03 18:55:26 +0300
commit7eea4dbec17be7f5e49b6e9aa5b0ffc3daf3b523 (patch)
tree019f1fec1e53454eb62438334cd423d498e71f7d
parent21d247dd213ec21fa25018e5f8d7f2045c6b1fa4 (diff)
ddr: apn806: add init value for electrical configurations
add new topology struct for electrical configuration in mv_ddr, with which the customers can set all electrical values in ATF according to their board topology. initialize these values for the current apn806 boards Change-Id: I740c07cec6da77eda70b49c0549fbe5c7c9fe772 Signed-off-by: Terry Zhou <bjzhou@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/56041 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
Diffstat
-rw-r--r--plat/marvell/a8k/a3900_z1/board/dram_port.c23
-rw-r--r--plat/marvell/a8k/a70x0/board/dram_port.c23
-rw-r--r--plat/marvell/a8k/a70x0_amc/board/dram_port.c23
-rw-r--r--plat/marvell/a8k/a70x0_cust/board/dram_port.c23
-rw-r--r--plat/marvell/a8k/a70x0_pcac/board/dram_port.c23
-rw-r--r--plat/marvell/a8k/a80x0/board/dram_port.c23
-rw-r--r--plat/marvell/a8k/a80x0_mcbin/board/dram_port.c23
-rw-r--r--plat/marvell/a8k/a80x0_ocp/board/dram_port.c23
8 files changed, 176 insertions, 8 deletions
diff --git a/plat/marvell/a8k/a3900_z1/board/dram_port.c b/plat/marvell/a8k/a3900_z1/board/dram_port.c
index 3677d22e..5cf19f44 100644
--- a/plat/marvell/a8k/a3900_z1/board/dram_port.c
+++ b/plat/marvell/a8k/a3900_z1/board/dram_port.c
@@ -46,7 +46,28 @@ static struct mv_ddr_topology_map board_topology_map = {
BUS_MASK_32BIT, /* subphys mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
{ {0} }, /* raw spd data */
- {0} /* timing parameters */
+ {0}, /* timing parameters */
+ { /* electrical configuration */
+ { /* memory electrical configuration */
+ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
+ MV_DDR_RTT_NOM_PARK_RZQ_DIV1, /* rtt_park */
+ MV_DDR_RTT_WR_RZQ_DIV2, /* rtt_wr */
+ MV_DDR_DIC_RZQ_DIV7 /* dic */
+ },
+ { /* phy electrical configuration */
+ MV_DDR_OHM_30, /* data_drv_p */
+ MV_DDR_OHM_30, /* data_drv_n */
+ MV_DDR_OHM_30, /* ctrl_drv_p */
+ MV_DDR_OHM_30, /* ctrl_drv_n */
+ MV_DDR_OHM_60, /* odt_p */
+ MV_DDR_OHM_60 /* odt_n */
+ },
+ { /* mac electrical configuration */
+ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
+ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
+ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
+ },
+ }
};
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
diff --git a/plat/marvell/a8k/a70x0/board/dram_port.c b/plat/marvell/a8k/a70x0/board/dram_port.c
index 755f7853..624329f7 100644
--- a/plat/marvell/a8k/a70x0/board/dram_port.c
+++ b/plat/marvell/a8k/a70x0/board/dram_port.c
@@ -46,7 +46,28 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_32BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
{ {0} }, /* raw spd data */
- {0} /* timing parameters */
+ {0}, /* timing parameters */
+ { /* electrical configuration */
+ { /* memory electrical configuration */
+ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
+ MV_DDR_RTT_NOM_PARK_RZQ_DIV1, /* rtt_park */
+ MV_DDR_RTT_WR_RZQ_DIV2, /* rtt_wr */
+ MV_DDR_DIC_RZQ_DIV7 /* dic */
+ },
+ { /* phy electrical configuration */
+ MV_DDR_OHM_30, /* data_drv_p */
+ MV_DDR_OHM_30, /* data_drv_n */
+ MV_DDR_OHM_30, /* ctrl_drv_p */
+ MV_DDR_OHM_30, /* ctrl_drv_n */
+ MV_DDR_OHM_120, /* odt_p */
+ MV_DDR_OHM_120 /* odt_n */
+ },
+ { /* mac electrical configuration */
+ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
+ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
+ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
+ },
+ }
};
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
diff --git a/plat/marvell/a8k/a70x0_amc/board/dram_port.c b/plat/marvell/a8k/a70x0_amc/board/dram_port.c
index 6511b8ba..7ccffedc 100644
--- a/plat/marvell/a8k/a70x0_amc/board/dram_port.c
+++ b/plat/marvell/a8k/a70x0_amc/board/dram_port.c
@@ -46,7 +46,28 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_32BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
{ {0} }, /* raw spd data */
- {0} /* timing parameters */
+ {0}, /* timing parameters */
+ { /* electrical configuration */
+ { /* memory electrical configuration */
+ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
+ MV_DDR_RTT_NOM_PARK_RZQ_DIV1, /* rtt_park */
+ MV_DDR_RTT_WR_RZQ_DIV2, /* rtt_wr */
+ MV_DDR_DIC_RZQ_DIV7 /* dic */
+ },
+ { /* phy electrical configuration */
+ MV_DDR_OHM_30, /* data_drv_p */
+ MV_DDR_OHM_30, /* data_drv_n */
+ MV_DDR_OHM_30, /* ctrl_drv_p */
+ MV_DDR_OHM_30, /* ctrl_drv_n */
+ MV_DDR_OHM_120, /* odt_p */
+ MV_DDR_OHM_120 /* odt_n */
+ },
+ { /* mac electrical configuration */
+ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
+ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
+ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
+ },
+ }
};
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
diff --git a/plat/marvell/a8k/a70x0_cust/board/dram_port.c b/plat/marvell/a8k/a70x0_cust/board/dram_port.c
index d5ac009c..53d5bd62 100644
--- a/plat/marvell/a8k/a70x0_cust/board/dram_port.c
+++ b/plat/marvell/a8k/a70x0_cust/board/dram_port.c
@@ -39,7 +39,28 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_32BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
{ {0} }, /* raw spd data */
- {0} /* timing parameters */
+ {0}, /* timing parameters */
+ { /* electrical configuration */
+ { /* memory electrical configuration */
+ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
+ MV_DDR_RTT_NOM_PARK_RZQ_DIV1, /* rtt_park */
+ MV_DDR_RTT_WR_RZQ_DIV2, /* rtt_wr */
+ MV_DDR_DIC_RZQ_DIV7 /* dic */
+ },
+ { /* phy electrical configuration */
+ MV_DDR_OHM_30, /* data_drv_p */
+ MV_DDR_OHM_30, /* data_drv_n */
+ MV_DDR_OHM_30, /* ctrl_drv_p */
+ MV_DDR_OHM_30, /* ctrl_drv_n */
+ MV_DDR_OHM_60, /* odt_p */
+ MV_DDR_OHM_60 /* odt_n */
+ },
+ { /* mac electrical configuration */
+ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
+ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
+ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
+ },
+ }
};
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
diff --git a/plat/marvell/a8k/a70x0_pcac/board/dram_port.c b/plat/marvell/a8k/a70x0_pcac/board/dram_port.c
index 89968de6..17619a05 100644
--- a/plat/marvell/a8k/a70x0_pcac/board/dram_port.c
+++ b/plat/marvell/a8k/a70x0_pcac/board/dram_port.c
@@ -46,7 +46,28 @@ static struct mv_ddr_topology_map board_topology_map = {
BUS_MASK_32BIT, /* subphys mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
{ {0} }, /* raw spd data */
- {0} /* timing parameters */
+ {0}, /* timing parameters */
+ { /* electrical configuration */
+ { /* memory electrical configuration */
+ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
+ MV_DDR_RTT_NOM_PARK_RZQ_DIV1, /* rtt_park */
+ MV_DDR_RTT_WR_RZQ_DIV2, /* rtt_wr */
+ MV_DDR_DIC_RZQ_DIV7 /* dic */
+ },
+ { /* phy electrical configuration */
+ MV_DDR_OHM_30, /* data_drv_p */
+ MV_DDR_OHM_30, /* data_drv_n */
+ MV_DDR_OHM_30, /* ctrl_drv_p */
+ MV_DDR_OHM_30, /* ctrl_drv_n */
+ MV_DDR_OHM_60, /* odt_p */
+ MV_DDR_OHM_60 /* odt_n */
+ },
+ { /* mac electrical configuration */
+ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
+ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
+ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
+ },
+ }
};
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
diff --git a/plat/marvell/a8k/a80x0/board/dram_port.c b/plat/marvell/a8k/a80x0/board/dram_port.c
index a82776cf..1c8044f6 100644
--- a/plat/marvell/a8k/a80x0/board/dram_port.c
+++ b/plat/marvell/a8k/a80x0/board/dram_port.c
@@ -53,7 +53,28 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_64BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
MV_DDR_CFG_SPD, /* ddr configuration data source */
{ {0} }, /* raw spd data */
- {0} /* timing parameters */
+ {0}, /* timing parameters */
+ { /* electrical configuration */
+ { /* memory electrical configuration */
+ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
+ MV_DDR_RTT_NOM_PARK_RZQ_DIV1, /* rtt_park */
+ MV_DDR_RTT_WR_RZQ_DIV2, /* rtt_wr */
+ MV_DDR_DIC_RZQ_DIV7 /* dic */
+ },
+ { /* phy electrical configuration */
+ MV_DDR_OHM_30, /* data_drv_p */
+ MV_DDR_OHM_30, /* data_drv_n */
+ MV_DDR_OHM_30, /* ctrl_drv_p */
+ MV_DDR_OHM_30, /* ctrl_drv_n */
+ MV_DDR_OHM_60, /* odt_p */
+ MV_DDR_OHM_60 /* odt_n */
+ },
+ { /* mac electrical configuration */
+ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
+ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
+ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
+ },
+ }
};
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
diff --git a/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c b/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c
index 6d60f098..c961db56 100644
--- a/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c
+++ b/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c
@@ -47,7 +47,28 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_64BIT_BUS_MASK, /* subphys mask */
MV_DDR_CFG_SPD, /* ddr configuration data source */
{ {0} }, /* raw spd data */
- {0} /* timing parameters */
+ {0}, /* timing parameters */
+ { /* electrical configuration */
+ { /* memory electrical configuration */
+ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
+ MV_DDR_RTT_NOM_PARK_RZQ_DIV1, /* rtt_park */
+ MV_DDR_RTT_WR_RZQ_DIV2, /* rtt_wr */
+ MV_DDR_DIC_RZQ_DIV7 /* dic */
+ },
+ { /* phy electrical configuration */
+ MV_DDR_OHM_30, /* data_drv_p */
+ MV_DDR_OHM_30, /* data_drv_n */
+ MV_DDR_OHM_30, /* ctrl_drv_p */
+ MV_DDR_OHM_30, /* ctrl_drv_n */
+ MV_DDR_OHM_60, /* odt_p */
+ MV_DDR_OHM_60 /* odt_n */
+ },
+ { /* mac electrical configuration */
+ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
+ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
+ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
+ },
+ }
};
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
diff --git a/plat/marvell/a8k/a80x0_ocp/board/dram_port.c b/plat/marvell/a8k/a80x0_ocp/board/dram_port.c
index ef83d16a..60f60732 100644
--- a/plat/marvell/a8k/a80x0_ocp/board/dram_port.c
+++ b/plat/marvell/a8k/a80x0_ocp/board/dram_port.c
@@ -39,7 +39,28 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_64BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
{ {0} }, /* raw spd data */
- {0} /* timing parameters */
+ {0}, /* timing parameters */
+ { /* electrical configuration */
+ { /* memory electrical configuration */
+ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
+ MV_DDR_RTT_NOM_PARK_RZQ_DIV1, /* rtt_park */
+ MV_DDR_RTT_WR_RZQ_DIV2, /* rtt_wr */
+ MV_DDR_DIC_RZQ_DIV7 /* dic */
+ },
+ { /* phy electrical configuration */
+ MV_DDR_OHM_30, /* data_drv_p */
+ MV_DDR_OHM_30, /* data_drv_n */
+ MV_DDR_OHM_30, /* ctrl_drv_p */
+ MV_DDR_OHM_30, /* ctrl_drv_n */
+ MV_DDR_OHM_60, /* odt_p */
+ MV_DDR_OHM_60 /* odt_n */
+ },
+ { /* mac electrical configuration */
+ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
+ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
+ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
+ },
+ }
};
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
generated by cgit (git 2.34.1) at 2025-07-23 17:51:20 +0000