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| author | Achin Gupta <achin.gupta@arm.com> | 2015-03-09 21:54:40 +0000 |
|---|---|---|
| committer | Achin Gupta <achin.gupta@arm.com> | 2015-03-20 08:52:13 +0000 |
| commit | 8cfc3fd2954380afdea0590b359a665102ea7ef3 (patch) | |
| tree | 610f67ac719bc90062601287b8a65767c9c8cbd6 /lib/stdlib/mem.c | |
| parent | 3b982be3b374cdc4947e23dd122f748dc7680d09 (diff) | |
Set group status of PPIs and SGIs correctly on GICv3 systems
On a GICv2 system, the group status of PPIs and SGIs is set in the GICD_IGROUPR0
register. On a GICv3 system, if affinity routing is enabled for the non-secure
state, then the group status of PPIs and SGIs should be set in the GICR_IGROUPR0
register. ARM Trusted firmware sets the group status using the GICv2
sequence. On a GICv3 system, if the group status of an interrupt is set to Group
1 through a write to the GICD_IGROUPR0, then the GICR_IGROUPR0 is updated as
well.
The current sequence is incorrect since it first marks all PPIs and SGIs as
Group 1. It then clears the bits in GICD_IGROUPR0 corresponding to secure
interrupts to set their group status to Group 0. This operation is a no-op. It
leaves the secure generic timer interrupt (#29) used by the TSP marked as Group
1. This causes the interrupt to interfere with the execution of non-secure
software. Once an interrupt has been marked as Group 1, the GICR_IGROUPR0 should
be programmed to change its group status.
This patch rectifies this issue by setting the group status of only the
non-secure PPI and SGIs to Group 1 in the first place. GICD_IGROUPR0 resets to
0. So secure interrupts are marked as Group 0 by default.
Change-Id: I958b4b15f3e2b2444ce4c17764def36216498d00
Diffstat (limited to 'lib/stdlib/mem.c')
0 files changed, 0 insertions, 0 deletions