diff options
| author | Soby Mathew <soby.mathew@arm.com> | 2014-07-04 16:02:26 +0100 |
|---|---|---|
| committer | Soby Mathew <soby.mathew@arm.com> | 2014-07-31 10:09:58 +0100 |
| commit | fdfabec10ce9d6d56691007dce3bc2599baeb0f0 (patch) | |
| tree | 6a77ab51f2da53c76238602eb389770a3a0a86a7 /services/std_svc/psci | |
| parent | dd2bdee61682df0ec65dfc43371c126a86a30c30 (diff) | |
Optimize EL3 register state stored in cpu_context structure
This patch further optimizes the EL3 register state stored in
cpu_context. The 2 registers which are removed from cpu_context are:
* cntfrq_el0 is the system timer register which is writable
only in EL3 and it can be programmed during cold/warm boot. Hence
it need not be saved to cpu_context.
* cptr_el3 controls access to Trace, Floating-point, and Advanced
SIMD functionality and it is programmed every time during cold
and warm boot. The current BL3-1 implementation does not need to
modify the access controls during normal execution and hence
they are expected to remain static.
Fixes ARM-software/tf-issues#197
Change-Id: I599ceee3b73a7dcfd37069fd41b60e3d397a7b18
Diffstat (limited to 'services/std_svc/psci')
| -rw-r--r-- | services/std_svc/psci/psci_afflvl_suspend.c | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/services/std_svc/psci/psci_afflvl_suspend.c b/services/std_svc/psci/psci_afflvl_suspend.c index 1e60276c..70f90a15 100644 --- a/services/std_svc/psci/psci_afflvl_suspend.c +++ b/services/std_svc/psci/psci_afflvl_suspend.c @@ -34,6 +34,7 @@ #include <arch_helpers.h> #include <context.h> #include <context_mgmt.h> +#include <platform.h> #include <runtime_svc.h> #include <stddef.h> #include "psci_private.h" @@ -162,13 +163,6 @@ static int psci_afflvl0_suspend(aff_map_node_t *cpu_node, if (rc != PSCI_E_SUCCESS) return rc; - /* - * Arch. management: Save the EL3 state in the 'cpu_context' - * structure that has been allocated for this cpu, flush the - * L1 caches and exit intra-cluster coherency et al - */ - cm_el3_sysregs_context_save(NON_SECURE); - /* Set the secure world (EL3) re-entry point after BL1 */ psci_entrypoint = (unsigned long) psci_aff_suspend_finish_entry; @@ -414,6 +408,7 @@ static unsigned int psci_afflvl0_suspend_finish(aff_map_node_t *cpu_node) { unsigned int plat_state, state, rc; int32_t suspend_level; + uint64_t counter_freq; assert(cpu_node->level == MPIDR_AFFLVL0); @@ -445,7 +440,10 @@ static unsigned int psci_afflvl0_suspend_finish(aff_map_node_t *cpu_node) * structure for this cpu. */ psci_do_pwrup_cache_maintenance(); - cm_el3_sysregs_context_restore(NON_SECURE); + + /* Re-init the cntfrq_el0 register */ + counter_freq = plat_get_syscnt_freq(); + write_cntfrq_el0(counter_freq); /* * Call the cpu suspend finish handler registered by the Secure Payload |