diff options
32 files changed, 434 insertions, 102 deletions
@@ -60,6 +60,9 @@ CTX_INCLUDE_FPREGS := 0 # Determine the version of ARM GIC architecture to use for interrupt management # in EL3. The platform port can change this value if needed. ARM_GIC_ARCH := 2 +# Determine the version of ARM CCI product used in the platform. The platform +# port can change this value if needed. +ARM_CCI_PRODUCT_ID := 400 # Flag used to indicate if ASM_ASSERTION should be enabled for the build. # This defaults to being present in DEBUG builds only. ASM_ASSERTION := ${DEBUG} @@ -77,7 +80,9 @@ TRUSTED_BOARD_BOOT := 0 AUTH_MOD := none # Checkpatch ignores -CHECK_IGNORE = --ignore COMPLEX_MACRO --ignore GERRIT_CHANGE_ID +CHECK_IGNORE = --ignore COMPLEX_MACRO \ + --ignore GERRIT_CHANGE_ID \ + --ignore GIT_COMMIT_ID CHECKPATCH_ARGS = --no-tree --no-signoff ${CHECK_IGNORE} CHECKCODE_ARGS = --no-patch --no-tree --no-signoff ${CHECK_IGNORE} @@ -235,6 +240,9 @@ $(eval $(call add_define,CTX_INCLUDE_FPREGS)) # Process ARM_GIC_ARCH flag $(eval $(call add_define,ARM_GIC_ARCH)) +# Process ARM_CCI_PRODUCT_ID flag +$(eval $(call add_define,ARM_CCI_PRODUCT_ID)) + # Process ASM_ASSERTION flag $(eval $(call assert_boolean,ASM_ASSERTION)) $(eval $(call add_define,ASM_ASSERTION)) @@ -600,7 +608,7 @@ endif # Add the dependency on the certificates ifneq (${GENERATE_COT},0) - all: certificates + fip: certificates endif certificates: ${CRT_DEPS} ${CRTTOOL} check_bl30 check_bl33 @@ -625,16 +633,23 @@ cscope: ${Q}cscope -b -q -k help: - @echo "usage: ${MAKE} PLAT=<${HELP_PLATFORMS}> <all|bl1|bl2|bl31|distclean|clean|checkcodebase|checkpatch>" + @echo "usage: ${MAKE} PLAT=<${HELP_PLATFORMS}> [OPTIONS] [TARGET]" @echo "" @echo "PLAT is used to specify which platform you wish to build." @echo "If no platform is specified, PLAT defaults to: ${DEFAULT_PLAT}" @echo "" + @echo "Please refer to the User Guide for a list of all supported options." + @echo "Note that the build system doesn't track dependencies for build " + @echo "options. Therefore, if any of the build options are changed " + @echo "from a previous build, a clean build must be performed." + @echo "" @echo "Supported Targets:" - @echo " all Build the BL1, BL2 and BL31 binaries" + @echo " all Build all individual bootloader binaries" @echo " bl1 Build the BL1 binary" @echo " bl2 Build the BL2 binary" - @echo " bl31 Build the BL31 binary" + @echo " bl31 Build the BL3-1 binary" + @echo " bl32 Build the BL3-2 binary" + @echo " fip Build the Firmware Image Package (FIP)" @echo " checkcodebase Check the coding style of the entire source tree" @echo " checkpatch Check the coding style on changes in the current" @echo " branch against BASE_COMMIT (default origin/master)" @@ -644,7 +659,7 @@ help: @echo " certtool Build the Certificate generation tool" @echo " fiptool Build the Firmware Image Package(FIP) creation tool" @echo "" - @echo "note: most build targets require PLAT to be set to a specific platform." + @echo "Note: most build targets require PLAT to be set to a specific platform." @echo "" @echo "example: build all targets for the FVP platform:" @echo " CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp all" diff --git a/bl31/aarch64/bl31_arch_setup.c b/bl31/aarch64/bl31_arch_setup.c index a88b029e..edf10188 100644 --- a/bl31/aarch64/bl31_arch_setup.c +++ b/bl31/aarch64/bl31_arch_setup.c @@ -33,6 +33,7 @@ #include <assert.h> #include <bl_common.h> #include <bl31.h> +#include <cpu_data.h> #include <platform.h> /******************************************************************************* @@ -47,4 +48,7 @@ void bl31_arch_setup(void) /* Program the counter frequency */ write_cntfrq_el0(plat_get_syscnt_freq()); + + /* Initialize the cpu_ops pointer. */ + init_cpu_ops(); } diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index 01d7a7f5..186b1cbc 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -162,12 +162,6 @@ func bl31_entrypoint #endif /* --------------------------------------------- - * Initialize the cpu_ops pointer. - * --------------------------------------------- - */ - bl init_cpu_ops - - /* --------------------------------------------- * Use SP_EL0 for the C runtime stack. * --------------------------------------------- */ diff --git a/bl31/runtime_svc.c b/bl31/runtime_svc.c index c33748f9..fd64c824 100644 --- a/bl31/runtime_svc.c +++ b/bl31/runtime_svc.c @@ -103,8 +103,8 @@ void runtime_svc_init(void) */ rc = validate_rt_svc_desc(&rt_svc_descs[index]); if (rc) { - ERROR("Invalid runtime service descriptor 0x%x (%s)\n", - &rt_svc_descs[index], + ERROR("Invalid runtime service descriptor 0x%lx (%s)\n", + (uintptr_t) &rt_svc_descs[index], rt_svc_descs[index].name); goto error; } diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c index c6000e19..d8895b2f 100644 --- a/bl32/tsp/tsp_main.c +++ b/bl32/tsp/tsp_main.c @@ -109,9 +109,9 @@ uint64_t tsp_main(void) { NOTICE("TSP: %s\n", version_string); NOTICE("TSP: %s\n", build_message); - INFO("TSP: Total memory base : 0x%x\n", (unsigned long)BL32_TOTAL_BASE); - INFO("TSP: Total memory size : 0x%x bytes\n", - (unsigned long)(BL32_TOTAL_LIMIT - BL32_TOTAL_BASE)); + INFO("TSP: Total memory base : 0x%lx\n", BL32_TOTAL_BASE); + INFO("TSP: Total memory size : 0x%lx bytes\n", + BL32_TOTAL_LIMIT - BL32_TOTAL_BASE); uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); @@ -129,7 +129,7 @@ uint64_t tsp_main(void) #if LOG_LEVEL >= LOG_LEVEL_INFO spin_lock(&console_lock); - INFO("TSP: cpu 0x%x: %d smcs, %d erets %d cpu on requests\n", mpidr, + INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", mpidr, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count, tsp_stats[linear_id].cpu_on_count); @@ -158,8 +158,8 @@ tsp_args_t *tsp_cpu_on_main(void) #if LOG_LEVEL >= LOG_LEVEL_INFO spin_lock(&console_lock); - INFO("TSP: cpu 0x%x turned on\n", mpidr); - INFO("TSP: cpu 0x%x: %d smcs, %d erets %d cpu on requests\n", mpidr, + INFO("TSP: cpu 0x%lx turned on\n", mpidr); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", mpidr, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count, tsp_stats[linear_id].cpu_on_count); @@ -199,8 +199,8 @@ tsp_args_t *tsp_cpu_off_main(uint64_t arg0, #if LOG_LEVEL >= LOG_LEVEL_INFO spin_lock(&console_lock); - INFO("TSP: cpu 0x%x off request\n", mpidr); - INFO("TSP: cpu 0x%x: %d smcs, %d erets %d cpu off requests\n", mpidr, + INFO("TSP: cpu 0x%lx off request\n", mpidr); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n", mpidr, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count, tsp_stats[linear_id].cpu_off_count); @@ -242,7 +242,7 @@ tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0, #if LOG_LEVEL >= LOG_LEVEL_INFO spin_lock(&console_lock); - INFO("TSP: cpu 0x%x: %d smcs, %d erets %d cpu suspend requests\n", + INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n", mpidr, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count, @@ -281,9 +281,9 @@ tsp_args_t *tsp_cpu_resume_main(uint64_t suspend_level, #if LOG_LEVEL >= LOG_LEVEL_INFO spin_lock(&console_lock); - INFO("TSP: cpu 0x%x resumed. suspend level %d\n", + INFO("TSP: cpu 0x%lx resumed. suspend level %ld\n", mpidr, suspend_level); - INFO("TSP: cpu 0x%x: %d smcs, %d erets %d cpu suspend requests\n", + INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n", mpidr, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count, @@ -316,8 +316,8 @@ tsp_args_t *tsp_system_off_main(uint64_t arg0, #if LOG_LEVEL >= LOG_LEVEL_INFO spin_lock(&console_lock); - INFO("TSP: cpu 0x%x SYSTEM_OFF request\n", mpidr); - INFO("TSP: cpu 0x%x: %d smcs, %d erets requests\n", mpidr, + INFO("TSP: cpu 0x%lx SYSTEM_OFF request\n", mpidr); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", mpidr, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count); spin_unlock(&console_lock); @@ -349,8 +349,8 @@ tsp_args_t *tsp_system_reset_main(uint64_t arg0, #if LOG_LEVEL >= LOG_LEVEL_INFO spin_lock(&console_lock); - INFO("TSP: cpu 0x%x SYSTEM_RESET request\n", mpidr); - INFO("TSP: cpu 0x%x: %d smcs, %d erets requests\n", mpidr, + INFO("TSP: cpu 0x%lx SYSTEM_RESET request\n", mpidr); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", mpidr, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count); spin_unlock(&console_lock); @@ -384,10 +384,10 @@ tsp_args_t *tsp_smc_handler(uint64_t func, tsp_stats[linear_id].smc_count++; tsp_stats[linear_id].eret_count++; - INFO("TSP: cpu 0x%x received %s smc 0x%x\n", read_mpidr(), + INFO("TSP: cpu 0x%lx received %s smc 0x%lx\n", mpidr, ((func >> 31) & 1) == 1 ? "fast" : "standard", func); - INFO("TSP: cpu 0x%x: %d smcs, %d erets\n", mpidr, + INFO("TSP: cpu 0x%lx: %d smcs, %d erets\n", mpidr, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count); diff --git a/docs/user-guide.md b/docs/user-guide.md index 1badc0c8..411a8702 100644 --- a/docs/user-guide.md +++ b/docs/user-guide.md @@ -59,6 +59,9 @@ The following tools are required to use the ARM Trusted Firmware: wget http://releases.linaro.org/14.07/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.9-2014.07_linux.tar.xz tar -xf gcc-linaro-aarch64-none-elf-4.9-2014.07_linux.tar.xz +* `libssl-dev` package to build the certificate generation tool when support + for Trusted Board Boot is needed. + * (Optional) For debugging, ARM [Development Studio 5 (DS-5)][DS-5] v5.20. @@ -218,6 +221,10 @@ performed. driver for implementing the platform GIC API. This API is used by the interrupt management framework. Default is 2 (that is, version 2.0). +* `ARM_CCI_PRODUCT_ID`: Choice of ARM CCI product used by the platform. This + is used to determine the number of valid slave interfaces available in the + ARM CCI driver. Default is 400 (that is, CCI-400). + * `IMF_READ_INTERRUPT_ID`: Boolean flag used by the interrupt management framework to enable passing of the interrupt id to its handler. The id is read using a platform GIC API. `INTR_ID_UNAVAILABLE` is passed instead if diff --git a/drivers/arm/cci/cci.c b/drivers/arm/cci/cci.c new file mode 100644 index 00000000..44916d4b --- /dev/null +++ b/drivers/arm/cci/cci.c @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch.h> +#include <assert.h> +#include <cci.h> +#include <debug.h> +#include <mmio.h> + +static unsigned long g_cci_base; +static unsigned int g_max_master_id; +static const int *g_cci_slave_if_map; + +#if DEBUG +static int validate_cci_map(const int *map) +{ + unsigned int valid_cci_map = 0; + int slave_if_id; + int i; + + /* Validate the map */ + for (i = 0; i <= g_max_master_id; i++) { + slave_if_id = map[i]; + + if (slave_if_id < 0) + continue; + + if (slave_if_id >= CCI_SLAVE_INTERFACE_COUNT) { + tf_printf("Slave interface ID is invalid\n"); + return 0; + } + + if (valid_cci_map & (1 << slave_if_id)) { + tf_printf("Multiple masters are assigned same" + " slave interface ID\n"); + return 0; + } + valid_cci_map |= 1 << slave_if_id; + } + + if (!valid_cci_map) { + tf_printf("No master is assigned a valid slave interface\n"); + return 0; + } + + return 1; +} +#endif /* DEBUG */ + +void cci_init(unsigned long cci_base, + const int *map, + unsigned int num_cci_masters) +{ + assert(map); + assert(cci_base); + + g_cci_base = cci_base; + + /* + * Master Id's are assigned from zero, So in an array of size n + * the max master id is (n - 1). + */ + g_max_master_id = num_cci_masters - 1; + + assert(validate_cci_map(map)); + g_cci_slave_if_map = map; +} + +void cci_enable_snoop_dvm_reqs(unsigned int master_id) +{ + int slave_if_id; + + assert(g_cci_base); + assert(master_id <= g_max_master_id); + + slave_if_id = g_cci_slave_if_map[master_id]; + assert((slave_if_id < CCI_SLAVE_INTERFACE_COUNT) && (slave_if_id >= 0)); + + /* + * Enable Snoops and DVM messages, no need for Read/Modify/Write as + * rest of bits are write ignore + */ + mmio_write_32(g_cci_base + + SLAVE_IFACE_OFFSET(slave_if_id) + + SNOOP_CTRL_REG, DVM_EN_BIT | SNOOP_EN_BIT); + + /* Wait for the dust to settle down */ + while (mmio_read_32(g_cci_base + STATUS_REG) & CHANGE_PENDING_BIT) + ; +} + +void cci_disable_snoop_dvm_reqs(unsigned int master_id) +{ + int slave_if_id; + + assert(g_cci_base); + assert(master_id <= g_max_master_id); + + slave_if_id = g_cci_slave_if_map[master_id]; + assert((slave_if_id < CCI_SLAVE_INTERFACE_COUNT) && (slave_if_id >= 0)); + + /* + * Disable Snoops and DVM messages, no need for Read/Modify/Write as + * rest of bits are write ignore. + */ + mmio_write_32(g_cci_base + + SLAVE_IFACE_OFFSET(slave_if_id) + + SNOOP_CTRL_REG, ~(DVM_EN_BIT | SNOOP_EN_BIT)); + + /* Wait for the dust to settle down */ + while (mmio_read_32(g_cci_base + STATUS_REG) & CHANGE_PENDING_BIT) + ; +} + diff --git a/drivers/arm/cci400/cci400.c b/drivers/arm/cci400/cci400.c index 6a8737a5..f832af82 100644 --- a/drivers/arm/cci400/cci400.c +++ b/drivers/arm/cci400/cci400.c @@ -31,6 +31,7 @@ #include <arch.h> #include <assert.h> #include <cci400.h> +#include <debug.h> #include <mmio.h> #define MAX_CLUSTERS 2 @@ -55,6 +56,9 @@ void cci_init(unsigned long cci_base, assert((slave_iface3_cluster_ix >= 0) || (slave_iface3_cluster_ix >= 0)); + WARN("Please migrate to common cci driver, This driver will be" \ + " deprecated in future\n"); + cci_base_addr = cci_base; if (slave_iface3_cluster_ix >= 0) cci_cluster_ix_to_iface[slave_iface3_cluster_ix] = diff --git a/drivers/io/io_fip.c b/drivers/io/io_fip.c index 0cec8044..9dcd901e 100644 --- a/drivers/io/io_fip.c +++ b/drivers/io/io_fip.c @@ -143,7 +143,7 @@ static int file_to_uuid(const char *filename, uuid_t *uuid) int i; int status = -EINVAL; - for (i = 0; i < (sizeof(name_uuid) / sizeof(name_uuid[0])); i++) { + for (i = 0; i < ARRAY_SIZE(name_uuid); i++) { if (strcmp(filename, name_uuid[i].name) == 0) { copy_uuid(uuid, &name_uuid[i].uuid); status = 0; diff --git a/include/bl31/cpu_data.h b/include/bl31/cpu_data.h index 1926e292..50f509bb 100644 --- a/include/bl31/cpu_data.h +++ b/include/bl31/cpu_data.h @@ -117,6 +117,7 @@ static inline struct cpu_data *_cpu_data(void) *************************************************************************/ void init_cpu_data_ptr(void); +void init_cpu_ops(void); #define get_cpu_data(_m) _cpu_data()->_m #define set_cpu_data(_m, _v) _cpu_data()->_m = _v diff --git a/include/common/bl_common.h b/include/common/bl_common.h index 0959c893..b36c9d35 100644 --- a/include/common/bl_common.h +++ b/include/common/bl_common.h @@ -108,6 +108,8 @@ #include <stdint.h> #include <stddef.h> +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + /******************************************************************************* * Structure used for telling the next BL how much of a particular type of * memory is available for its use and how much is already used. diff --git a/include/common/debug.h b/include/common/debug.h index a8dcb8da..d198c321 100644 --- a/include/common/debug.h +++ b/include/common/debug.h @@ -84,6 +84,6 @@ void __dead2 do_panic(void); #define panic() do_panic() -void tf_printf(const char *fmt, ...); +void tf_printf(const char *fmt, ...) __printflike(1, 2); #endif /* __DEBUG_H__ */ diff --git a/include/drivers/arm/cci.h b/include/drivers/arm/cci.h new file mode 100644 index 00000000..2401e85a --- /dev/null +++ b/include/drivers/arm/cci.h @@ -0,0 +1,157 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CCI_H__ +#define __CCI_H__ + +/* Slave interface offsets from PERIPHBASE */ +#define SLAVE_IFACE6_OFFSET 0x7000 +#define SLAVE_IFACE5_OFFSET 0x6000 +#define SLAVE_IFACE4_OFFSET 0x5000 +#define SLAVE_IFACE3_OFFSET 0x4000 +#define SLAVE_IFACE2_OFFSET 0x3000 +#define SLAVE_IFACE1_OFFSET 0x2000 +#define SLAVE_IFACE0_OFFSET 0x1000 +#define SLAVE_IFACE_OFFSET(index) (SLAVE_IFACE0_OFFSET + \ + (0x1000 * (index))) + +/* Slave interface event and count register offsets from PERIPHBASE */ +#define EVENT_SELECT7_OFFSET 0x80000 +#define EVENT_SELECT6_OFFSET 0x70000 +#define EVENT_SELECT5_OFFSET 0x60000 +#define EVENT_SELECT4_OFFSET 0x50000 +#define EVENT_SELECT3_OFFSET 0x40000 +#define EVENT_SELECT2_OFFSET 0x30000 +#define EVENT_SELECT1_OFFSET 0x20000 +#define EVENT_SELECT0_OFFSET 0x10000 +#define EVENT_OFFSET(index) (EVENT_SELECT0_OFFSET + \ + (0x10000 * (index))) + +/* Control and ID register offsets */ +#define CTRL_OVERRIDE_REG 0x0 +#define SECURE_ACCESS_REG 0x8 +#define STATUS_REG 0xc +#define IMPRECISE_ERR_REG 0x10 +#define PERFMON_CTRL_REG 0x100 +#define IFACE_MON_CTRL_REG 0x104 + +/* Component and peripheral ID registers */ +#define PERIPHERAL_ID0 0xFE0 +#define PERIPHERAL_ID1 0xFE4 +#define PERIPHERAL_ID2 0xFE8 +#define PERIPHERAL_ID3 0xFEC +#define PERIPHERAL_ID4 0xFD0 +#define PERIPHERAL_ID5 0xFD4 +#define PERIPHERAL_ID6 0xFD8 +#define PERIPHERAL_ID7 0xFDC + +#define COMPONENT_ID0 0xFF0 +#define COMPONENT_ID1 0xFF4 +#define COMPONENT_ID2 0xFF8 +#define COMPONENT_ID3 0xFFC +#define COMPONENT_ID4 0x1000 +#define COMPONENT_ID5 0x1004 +#define COMPONENT_ID6 0x1008 +#define COMPONENT_ID7 0x100C + +/* Slave interface register offsets */ +#define SNOOP_CTRL_REG 0x0 +#define SH_OVERRIDE_REG 0x4 +#define READ_CHNL_QOS_VAL_OVERRIDE_REG 0x100 +#define WRITE_CHNL_QOS_VAL_OVERRIDE_REG 0x104 +#define MAX_OT_REG 0x110 + +/* Snoop Control register bit definitions */ +#define DVM_EN_BIT (1 << 1) +#define SNOOP_EN_BIT (1 << 0) +#define SUPPORT_SNOOPS (1 << 30) +#define SUPPORT_DVM (1 << 31) + +/* Status register bit definitions */ +#define CHANGE_PENDING_BIT (1 << 0) + +/* Event and count register offsets */ +#define EVENT_SELECT_REG 0x0 +#define EVENT_COUNT_REG 0x4 +#define COUNT_CNTRL_REG 0x8 +#define COUNT_OVERFLOW_REG 0xC + +/* Slave interface monitor registers */ +#define INT_MON_REG_SI0 0x90000 +#define INT_MON_REG_SI1 0x90004 +#define INT_MON_REG_SI2 0x90008 +#define INT_MON_REG_SI3 0x9000C +#define INT_MON_REG_SI4 0x90010 +#define INT_MON_REG_SI5 0x90014 +#define INT_MON_REG_SI6 0x90018 + +/* Master interface monitor registers */ +#define INT_MON_REG_MI0 0x90100 +#define INT_MON_REG_MI1 0x90104 +#define INT_MON_REG_MI2 0x90108 +#define INT_MON_REG_MI3 0x9010c +#define INT_MON_REG_MI4 0x90110 +#define INT_MON_REG_MI5 0x90114 + +#define SLAVE_IF_UNUSED -1 + +#if ARM_CCI_PRODUCT_ID == 400 + #define CCI_SLAVE_INTERFACE_COUNT 5 +#elif ARM_CCI_PRODUCT_ID == 500 + #define CCI_SLAVE_INTERFACE_COUNT 7 +#else + #error "Invalid CCI product or CCI not supported" +#endif + +#ifndef __ASSEMBLY__ + +#include <stdint.h> + +/* Function declarations */ + +/* + * The ARM CCI driver needs the following: + * 1. Base address of the CCI-500/CCI-400 + * 2. An array of map between AMBA 4 master ids and ACE/ACE lite slave + * interfaces. + * 3. Size of the array. + * + * SLAVE_IF_UNUSED should be used in the map to represent no AMBA 4 master exists + * for that interface. + */ +void cci_init(unsigned long cci_base, + const int *map, + unsigned int num_cci_masters); + +void cci_enable_snoop_dvm_reqs(unsigned int master_id); +void cci_disable_snoop_dvm_reqs(unsigned int master_id); + +#endif /* __ASSEMBLY__ */ +#endif /* __CCI_H__ */ diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 52916846..5e216737 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -61,6 +61,14 @@ #define MPIDR_AFFLVL1 1 #define MPIDR_AFFLVL2 2 #define MPIDR_AFFLVL3 3 +#define MPIDR_AFFLVL0_VAL(mpidr) \ + ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) +#define MPIDR_AFFLVL1_VAL(mpidr) \ + ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) +#define MPIDR_AFFLVL2_VAL(mpidr) \ + ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) +#define MPIDR_AFFLVL3_VAL(mpidr) \ + ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) /* * The MPIDR_MAX_AFFLVL count starts from 0. Take care to * add one while using this macro to define array sizes. diff --git a/include/stdlib/stdio.h b/include/stdlib/stdio.h index 60e081b4..57e5c7fa 100644 --- a/include/stdlib/stdio.h +++ b/include/stdlib/stdio.h @@ -58,12 +58,13 @@ typedef __ssize_t ssize_t; #define EOF (-1) -int printf(const char * __restrict, ...); +int printf(const char * __restrict, ...) __printflike(1, 2); int putchar(int); int puts(const char *); -int sprintf(char * __restrict, const char * __restrict, ...); +int sprintf(char * __restrict, const char * __restrict, ...) + __printflike(2, 3); int vsprintf(char * __restrict, const char * __restrict, - __va_list); + __va_list) __printflike(2, 0); int sscanf(const char *__restrict, char const *__restrict, ...); diff --git a/lib/aarch64/xlat_tables.c b/lib/aarch64/xlat_tables.c index ddc9ba88..fa1a03da 100644 --- a/lib/aarch64/xlat_tables.c +++ b/lib/aarch64/xlat_tables.c @@ -31,6 +31,7 @@ #include <arch.h> #include <arch_helpers.h> #include <assert.h> +#include <bl_common.h> #include <cassert.h> #include <platform_def.h> #include <string.h> @@ -89,7 +90,7 @@ void mmap_add_region(unsigned long base_pa, unsigned long base_va, unsigned long size, unsigned attr) { mmap_region_t *mm = mmap; - mmap_region_t *mm_last = mm + sizeof(mmap) / sizeof(mmap[0]) - 1; + mmap_region_t *mm_last = mm + ARRAY_SIZE(mmap) - 1; unsigned long pa_end = base_pa + size - 1; unsigned long va_end = base_va + size - 1; diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S index bebe7c0a..24c283ab 100644 --- a/lib/cpus/aarch64/cpu_helpers.S +++ b/lib/cpus/aarch64/cpu_helpers.S @@ -110,7 +110,8 @@ func prepare_cluster_pwr_dwn /* * Initializes the cpu_ops_ptr if not already initialized - * in cpu_data. This can be called without a runtime stack. + * in cpu_data. This can be called without a runtime stack, but may + * only be called after the MMU is enabled. * clobbers: x0 - x6, x10 */ .globl init_cpu_ops @@ -125,18 +126,6 @@ func init_cpu_ops ASM_ASSERT(ne) #endif str x0, [x6, #CPU_DATA_CPU_OPS_PTR]! - - /* - * Make sure that any pre-fetched cache copies are invalidated. - * Ensure that we are running with cache disable else we - * invalidate our own update. - */ -#if ASM_ASSERTION - mrs x1, sctlr_el3 - tst x1, #SCTLR_C_BIT - ASM_ASSERT(eq) -#endif - dc ivac, x6 mov x30, x10 1: ret diff --git a/plat/fvp/aarch64/fvp_common.c b/plat/fvp/aarch64/fvp_common.c index fcda2a87..a8afb4e8 100644 --- a/plat/fvp/aarch64/fvp_common.c +++ b/plat/fvp/aarch64/fvp_common.c @@ -32,7 +32,7 @@ #include <arch_helpers.h> #include <arm_gic.h> #include <bl_common.h> -#include <cci400.h> +#include <cci.h> #include <debug.h> #include <mmio.h> #include <platform.h> @@ -115,7 +115,7 @@ const mmap_region_t fvp_mmap[] = { }; #endif -CASSERT((sizeof(fvp_mmap)/sizeof(fvp_mmap[0])) + FVP_BL_REGIONS \ +CASSERT(ARRAY_SIZE(fvp_mmap) + FVP_BL_REGIONS \ <= MAX_MMAP_REGIONS, assert_max_mmap_regions); /* Array of secure interrupts to be configured by the gic driver */ @@ -132,9 +132,6 @@ const unsigned int irq_sec_array[] = { IRQ_SEC_SGI_7 }; -const unsigned int num_sec_irqs = sizeof(irq_sec_array) / - sizeof(irq_sec_array[0]); - /******************************************************************************* * Macro generating the code for the function setting up the pagetables as per * the platform memory map & initialize the mmu, for the given exception level @@ -298,6 +295,12 @@ uint64_t plat_get_syscnt_freq(void) return counter_base_frequency; } +/* Map of CCI masters with the slave interfaces they are connected */ +static const int cci_map[] = { + CCI400_CLUSTER0_SL_IFACE_IX, + CCI400_CLUSTER1_SL_IFACE_IX +}; + void fvp_cci_init(void) { /* @@ -305,19 +308,20 @@ void fvp_cci_init(void) */ if (plat_config.flags & CONFIG_HAS_CCI) cci_init(CCI400_BASE, - CCI400_SL_IFACE3_CLUSTER_IX, - CCI400_SL_IFACE4_CLUSTER_IX); + cci_map, + ARRAY_SIZE(cci_map)); } void fvp_cci_enable(void) { - /* - * Enable CCI-400 coherency for this cluster. No need - * for locks as no other cpu is active at the - * moment - */ if (plat_config.flags & CONFIG_HAS_CCI) - cci_enable_cluster_coherency(read_mpidr()); + cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); +} + +void fvp_cci_disable(void) +{ + if (plat_config.flags & CONFIG_HAS_CCI) + cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); } void fvp_gic_init(void) @@ -326,7 +330,7 @@ void fvp_gic_init(void) plat_config.gicd_base, BASE_GICR_BASE, irq_sec_array, - num_sec_irqs); + ARRAY_SIZE(irq_sec_array)); } diff --git a/plat/fvp/fvp_def.h b/plat/fvp/fvp_def.h index e3442fce..a2f2da8c 100644 --- a/plat/fvp/fvp_def.h +++ b/plat/fvp/fvp_def.h @@ -236,8 +236,8 @@ * CCI-400 related constants ******************************************************************************/ #define CCI400_BASE 0x2c090000 -#define CCI400_SL_IFACE3_CLUSTER_IX 0 -#define CCI400_SL_IFACE4_CLUSTER_IX 1 +#define CCI400_CLUSTER0_SL_IFACE_IX 3 +#define CCI400_CLUSTER1_SL_IFACE_IX 4 /******************************************************************************* * GIC-400 & interrupt handling related constants diff --git a/plat/fvp/fvp_pm.c b/plat/fvp/fvp_pm.c index c15d845d..3737ecff 100644 --- a/plat/fvp/fvp_pm.c +++ b/plat/fvp/fvp_pm.c @@ -32,7 +32,7 @@ #include <arm_gic.h> #include <assert.h> #include <bakery_lock.h> -#include <cci400.h> +#include <cci.h> #include <debug.h> #include <mmio.h> #include <platform.h> @@ -82,8 +82,7 @@ static void fvp_cluster_pwrdwn_common(void) uint64_t mpidr = read_mpidr_el1(); /* Disable coherency if this cluster is to be turned off */ - if (get_plat_config()->flags & CONFIG_HAS_CCI) - cci_disable_cluster_coherency(mpidr); + fvp_cci_disable(); /* Program the power controller to turn the cluster off */ fvp_pwrc_write_pcoffr(mpidr); diff --git a/plat/fvp/fvp_private.h b/plat/fvp/fvp_private.h index 3949754b..4f60a161 100644 --- a/plat/fvp/fvp_private.h +++ b/plat/fvp/fvp_private.h @@ -138,6 +138,7 @@ int fvp_config_setup(void); void fvp_cci_init(void); void fvp_cci_enable(void); +void fvp_cci_disable(void); void fvp_gic_init(void); diff --git a/plat/fvp/include/plat_macros.S b/plat/fvp/include/plat_macros.S index f050261f..9e5ef4d5 100644 --- a/plat/fvp/include/plat_macros.S +++ b/plat/fvp/include/plat_macros.S @@ -27,7 +27,7 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ -#include <cci400.h> +#include <cci.h> #include <gic_v2.h> #include <plat_config.h> #include "../fvp_def.h" diff --git a/plat/fvp/platform.mk b/plat/fvp/platform.mk index bcee3286..7cf571e4 100644 --- a/plat/fvp/platform.mk +++ b/plat/fvp/platform.mk @@ -57,7 +57,7 @@ PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \ plat/common/aarch64/plat_common.c \ plat/fvp/fvp_io_storage.c -BL1_SOURCES += drivers/arm/cci400/cci400.c \ +BL1_SOURCES += drivers/arm/cci/cci.c \ lib/cpus/aarch64/aem_generic.S \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ @@ -72,7 +72,7 @@ BL2_SOURCES += drivers/arm/tzc400/tzc400.c \ plat/fvp/fvp_security.c \ plat/fvp/aarch64/fvp_common.c -BL31_SOURCES += drivers/arm/cci400/cci400.c \ +BL31_SOURCES += drivers/arm/cci/cci.c \ drivers/arm/gic/arm_gic.c \ drivers/arm/gic/gic_v2.c \ drivers/arm/gic/gic_v3.c \ diff --git a/plat/juno/aarch64/juno_common.c b/plat/juno/aarch64/juno_common.c index 6ea0b155..6b6e1851 100644 --- a/plat/juno/aarch64/juno_common.c +++ b/plat/juno/aarch64/juno_common.c @@ -32,6 +32,7 @@ #include <arm_gic.h> #include <assert.h> #include <bl_common.h> +#include <cci.h> #include <debug.h> #include <mmio.h> #include <platform.h> @@ -114,7 +115,7 @@ static const mmap_region_t juno_mmap[] = { }; #endif -CASSERT((sizeof(juno_mmap)/sizeof(juno_mmap[0])) + JUNO_BL_REGIONS \ +CASSERT(ARRAY_SIZE(juno_mmap) + JUNO_BL_REGIONS \ <= MAX_MMAP_REGIONS, assert_max_mmap_regions); /* Array of secure interrupts to be configured by the gic driver */ @@ -136,8 +137,17 @@ const unsigned int irq_sec_array[] = { IRQ_SEC_SGI_7 }; -const unsigned int num_sec_irqs = sizeof(irq_sec_array) / - sizeof(irq_sec_array[0]); +static const int cci_map[] = { + CCI400_CLUSTER0_SL_IFACE_IX, + CCI400_CLUSTER1_SL_IFACE_IX +}; + +void plat_cci_init(void) +{ + cci_init(CCI400_BASE, + cci_map, + ARRAY_SIZE(cci_map)); +} /******************************************************************************* * Macro generating the code for the function setting up the pagetables as per @@ -211,5 +221,9 @@ uint64_t plat_get_syscnt_freq(void) void plat_gic_init(void) { - arm_gic_init(GICC_BASE, GICD_BASE, 0, irq_sec_array, num_sec_irqs); + arm_gic_init(GICC_BASE, + GICD_BASE, + 0, + irq_sec_array, + ARRAY_SIZE(irq_sec_array)); } diff --git a/plat/juno/bl1_plat_setup.c b/plat/juno/bl1_plat_setup.c index 23e8592b..3b3471a8 100644 --- a/plat/juno/bl1_plat_setup.c +++ b/plat/juno/bl1_plat_setup.c @@ -31,7 +31,7 @@ #include <arch_helpers.h> #include <assert.h> #include <bl_common.h> -#include <cci400.h> +#include <cci.h> #include <console.h> #include <debug.h> #include <mmio.h> @@ -82,10 +82,8 @@ void bl1_early_platform_setup(void) * Enable CCI-400 for this cluster. No need for locks as no other cpu is * active at the moment */ - cci_init(CCI400_BASE, - CCI400_SL_IFACE3_CLUSTER_IX, - CCI400_SL_IFACE4_CLUSTER_IX); - cci_enable_cluster_coherency(read_mpidr()); + plat_cci_init(); + cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); /* Allow BL1 to see the whole Trusted RAM */ bl1_tzram_layout.total_base = TZRAM_BASE; @@ -99,7 +97,7 @@ void bl1_early_platform_setup(void) BL1_RAM_BASE, bl1_size); - INFO("BL1: 0x%lx - 0x%lx [size = %u]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, + INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, bl1_size); } diff --git a/plat/juno/bl31_plat_setup.c b/plat/juno/bl31_plat_setup.c index 1d337688..194d6205 100644 --- a/plat/juno/bl31_plat_setup.c +++ b/plat/juno/bl31_plat_setup.c @@ -33,7 +33,7 @@ #include <assert.h> #include <bl31.h> #include <bl_common.h> -#include <cci400.h> +#include <cci.h> #include <console.h> #include <mmio.h> #include <platform.h> @@ -123,9 +123,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, * a warm boot. BL1 should have already enabled CCI coherency for this * cluster during cold boot. */ - cci_init(CCI400_BASE, - CCI400_SL_IFACE3_CLUSTER_IX, - CCI400_SL_IFACE4_CLUSTER_IX); + plat_cci_init(); /* * Check params passed from BL2 should not be NULL, diff --git a/plat/juno/include/plat_macros.S b/plat/juno/include/plat_macros.S index a9d2466b..ac1077b2 100644 --- a/plat/juno/include/plat_macros.S +++ b/plat/juno/include/plat_macros.S @@ -28,7 +28,7 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#include <cci400.h> +#include <cci.h> #include <gic_v2.h> #include "platform_def.h" #include "../juno_def.h" diff --git a/plat/juno/juno_def.h b/plat/juno/juno_def.h index 62bdda3b..ab39f3ca 100644 --- a/plat/juno/juno_def.h +++ b/plat/juno/juno_def.h @@ -261,8 +261,8 @@ * CCI-400 related constants ******************************************************************************/ #define CCI400_BASE 0x2c090000 -#define CCI400_SL_IFACE3_CLUSTER_IX 1 -#define CCI400_SL_IFACE4_CLUSTER_IX 0 +#define CCI400_CLUSTER0_SL_IFACE_IX 4 +#define CCI400_CLUSTER1_SL_IFACE_IX 3 /******************************************************************************* * SCP <=> AP boot configuration diff --git a/plat/juno/juno_private.h b/plat/juno/juno_private.h index 9a5944ca..afb1bfcf 100644 --- a/plat/juno/juno_private.h +++ b/plat/juno/juno_private.h @@ -154,6 +154,7 @@ unsigned long plat_get_ns_image_entrypoint(void); unsigned long platform_get_stack(unsigned long mpidr); uint64_t plat_get_syscnt_freq(void); void plat_gic_init(void); +void plat_cci_init(void); /* Declarations for plat_topology.c */ int plat_setup_topology(void); diff --git a/plat/juno/plat_pm.c b/plat/juno/plat_pm.c index 47338cfc..953e5f72 100644 --- a/plat/juno/plat_pm.c +++ b/plat/juno/plat_pm.c @@ -31,8 +31,8 @@ #include <assert.h> #include <arch_helpers.h> #include <arm_gic.h> +#include <cci.h> #include <debug.h> -#include <cci400.h> #include <errno.h> #include <platform.h> #include <platform_def.h> @@ -159,8 +159,7 @@ void juno_affinst_on_finish(uint32_t afflvl, uint32_t state) * if this cluster was off. */ if (afflvl != MPIDR_AFFLVL0) - cci_enable_cluster_coherency(mpidr); - + cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); /* Enable the gic cpu interface */ arm_gic_cpuif_setup(); @@ -187,7 +186,7 @@ static void juno_power_down_common(uint32_t afflvl) /* Cluster is to be turned off, so disable coherency */ if (afflvl > MPIDR_AFFLVL0) { - cci_disable_cluster_coherency(read_mpidr_el1()); + cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); cluster_state = scpi_power_off; } diff --git a/plat/juno/platform.mk b/plat/juno/platform.mk index 8beaecf0..68778141 100644 --- a/plat/juno/platform.mk +++ b/plat/juno/platform.mk @@ -56,7 +56,7 @@ PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \ plat/common/plat_gic.c \ plat/juno/plat_io_storage.c -BL1_SOURCES += drivers/arm/cci400/cci400.c \ +BL1_SOURCES += drivers/arm/cci/cci.c \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ plat/common/aarch64/platform_up_stack.S \ @@ -75,7 +75,7 @@ BL2_SOURCES += drivers/arm/tzc400/tzc400.c \ plat/juno/scp_bootloader.c \ plat/juno/scpi.c -BL31_SOURCES += drivers/arm/cci400/cci400.c \ +BL31_SOURCES += drivers/arm/cci/cci.c \ drivers/arm/gic/arm_gic.c \ drivers/arm/gic/gic_v2.c \ drivers/arm/gic/gic_v3.c \ @@ -103,7 +103,7 @@ endif NEED_BL30 := yes # Enable workarounds for selected Cortex-A57 erratas. -ERRATA_A57_806969 := 1 +ERRATA_A57_806969 := 0 ERRATA_A57_813420 := 1 # Enable option to skip L1 data cache flush during the Cortex-A57 cluster diff --git a/services/std_svc/psci/psci_entry.S b/services/std_svc/psci/psci_entry.S index 3e67d344..fb3f0076 100644 --- a/services/std_svc/psci/psci_entry.S +++ b/services/std_svc/psci/psci_entry.S @@ -87,12 +87,6 @@ psci_aff_common_finish_entry: bl init_cpu_data_ptr /* --------------------------------------------- - * Initialize the cpu_ops pointer. - * --------------------------------------------- - */ - bl init_cpu_ops - - /* --------------------------------------------- * Set the exception vectors * --------------------------------------------- */ |