diff options
| -rw-r--r-- | common/runtime_svc.c | 3 | ||||
| -rw-r--r-- | docs/user-guide.md | 13 | ||||
| -rw-r--r-- | drivers/arm/gic/v3/gicv3_private.h | 2 | ||||
| -rw-r--r-- | include/drivers/arm/gicv3.h | 6 | ||||
| -rw-r--r-- | include/plat/arm/board/common/board_arm_def.h | 28 | ||||
| -rw-r--r-- | plat/arm/board/common/board_common.mk | 6 | ||||
| -rw-r--r-- | plat/arm/board/fvp/include/platform_def.h | 22 | ||||
| -rw-r--r-- | plat/arm/board/juno/include/platform_def.h | 58 | ||||
| -rw-r--r-- | plat/arm/board/juno/platform.mk | 2 | ||||
| -rw-r--r-- | plat/rockchip/common/pmusram/pmu_sram_cpus_on.S | 2 | ||||
| -rw-r--r-- | plat/rockchip/rk3399/drivers/pmu/pmu.c | 99 | ||||
| -rw-r--r-- | plat/rockchip/rk3399/drivers/pmu/pmu.h | 21 | ||||
| -rw-r--r-- | plat/rockchip/rk3399/drivers/soc/soc.c | 38 | ||||
| -rw-r--r-- | plat/rockchip/rk3399/rk3399_def.h | 82 |
14 files changed, 229 insertions, 153 deletions
diff --git a/common/runtime_svc.c b/common/runtime_svc.c index 7a5855b6..b8af6cd8 100644 --- a/common/runtime_svc.c +++ b/common/runtime_svc.c @@ -87,7 +87,8 @@ void runtime_svc_init(void) int rc = 0, index, start_idx, end_idx; /* Assert the number of descriptors detected are less than maximum indices */ - assert((RT_SVC_DECS_NUM >= 0) && (RT_SVC_DECS_NUM < MAX_RT_SVCS)); + assert((RT_SVC_DESCS_END >= RT_SVC_DESCS_START) && + (RT_SVC_DECS_NUM < MAX_RT_SVCS)); /* If no runtime services are implemented then simply bail out */ if (RT_SVC_DECS_NUM == 0) diff --git a/docs/user-guide.md b/docs/user-guide.md index 6f51295a..84908741 100644 --- a/docs/user-guide.md +++ b/docs/user-guide.md @@ -471,12 +471,13 @@ map is explained in the [Firmware Design]. match the frame used by the Non-Secure image (normally the Linux kernel). Default is true (access to the frame is allowed). -* `ARM_BOARD_OPTIMISE_MMAP`: Boolean option to enable or disable optimisation - of page table and MMU related macros `PLAT_ARM_MMAP_ENTRIES` and - `MAX_XLAT_TABLES`. By default this flag is 0, which means it uses the - default unoptimised values for these macros. ARM development platforms - that wish to optimise memory usage for page tables need to set this flag to 1 - and must override the related macros. +* `ARM_BOARD_OPTIMISE_MEM`: Boolean option to enable or disable optimisation + of the memory reserved for each image. This affects the maximum size of each + BL image as well as the number of allocated memory regions and translation + tables. By default this flag is 0, which means it uses the default + unoptimised values for these macros. ARM development platforms that wish to + optimise memory usage need to set this flag to 1 and must override the + related macros. * 'ARM_BL31_IN_DRAM': Boolean option to select loading of BL31 in TZC secured DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load diff --git a/drivers/arm/gic/v3/gicv3_private.h b/drivers/arm/gic/v3/gicv3_private.h index 5e2409fc..9aa83382 100644 --- a/drivers/arm/gic/v3/gicv3_private.h +++ b/drivers/arm/gic/v3/gicv3_private.h @@ -141,6 +141,7 @@ static inline unsigned int gicd_read_pidr2(uintptr_t base) static inline unsigned long long gicd_read_irouter(uintptr_t base, unsigned int id) { + assert(id >= MIN_SPI_ID); return mmio_read_64(base + GICD_IROUTER + (id << 3)); } @@ -148,6 +149,7 @@ static inline void gicd_write_irouter(uintptr_t base, unsigned int id, unsigned long long affinity) { + assert(id >= MIN_SPI_ID); mmio_write_64(base + GICD_IROUTER + (id << 3), affinity); } diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h index e915c072..b7ad7785 100644 --- a/include/drivers/arm/gicv3.h +++ b/include/drivers/arm/gicv3.h @@ -55,7 +55,11 @@ #define GICD_SETSPI_SR 0x50 #define GICD_CLRSPI_SR 0x50 #define GICD_IGRPMODR 0xd00 -#define GICD_IROUTER 0x6100 +/* + * GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt id and + * n >= 32, making the effective offset as 0x6100. + */ +#define GICD_IROUTER 0x6000 #define GICD_PIDR2_GICV3 0xffe8 #define IGRPMODR_SHIFT 5 diff --git a/include/plat/arm/board/common/board_arm_def.h b/include/plat/arm/board/common/board_arm_def.h index d70fbb46..ad82923e 100644 --- a/include/plat/arm/board/common/board_arm_def.h +++ b/include/plat/arm/board/common/board_arm_def.h @@ -61,10 +61,10 @@ /* * The constants below are not optimised for memory usage. Platforms that wish - * to optimise these constants should set `ARM_BOARD_OPTIMISE_MMAP` to 1 and + * to optimise these constants should set `ARM_BOARD_OPTIMISE_MEM` to 1 and * provide there own values. */ -#if !ARM_BOARD_OPTIMISE_MMAP +#if !ARM_BOARD_OPTIMISE_MEM /* * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the * plat_arm_mmap array defined for each BL stage. @@ -81,7 +81,29 @@ # define MAX_XLAT_TABLES 5 #endif -#endif /* ARM_BOARD_OPTIMISE_MMAP */ +/* + * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size + * plus a little space for growth. + */ +#define PLAT_ARM_MAX_BL1_RW_SIZE 0xA000 + +/* + * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a + * little space for growth. + */ +#if TRUSTED_BOARD_BOOT +# define PLAT_ARM_MAX_BL2_SIZE 0x1D000 +#else +# define PLAT_ARM_MAX_BL2_SIZE 0xF000 +#endif + +/* + * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a + * little space for growth. + */ +#define PLAT_ARM_MAX_BL31_SIZE 0x1D000 + +#endif /* ARM_BOARD_OPTIMISE_MEM */ #define MAX_IO_DEVICES 3 #define MAX_IO_HANDLES 4 diff --git a/plat/arm/board/common/board_common.mk b/plat/arm/board/common/board_common.mk index 6ddc0c92..a5636d5e 100644 --- a/plat/arm/board/common/board_common.mk +++ b/plat/arm/board/common/board_common.mk @@ -61,8 +61,8 @@ ifneq (${TRUSTED_BOARD_BOOT},0) endif # This flag controls whether memory usage needs to be optimised -ARM_BOARD_OPTIMISE_MMAP ?= 0 +ARM_BOARD_OPTIMISE_MEM ?= 0 # Process flags -$(eval $(call assert_boolean,ARM_BOARD_OPTIMISE_MMAP)) -$(eval $(call add_define,ARM_BOARD_OPTIMISE_MMAP)) +$(eval $(call assert_boolean,ARM_BOARD_OPTIMISE_MEM)) +$(eval $(call add_define,ARM_BOARD_OPTIMISE_MEM)) diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 1e906d82..d0898adc 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -146,26 +146,4 @@ #define PLAT_ARM_G0_IRQS ARM_G0_IRQS -/* - * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size - * plus a little space for growth. - */ -#define PLAT_ARM_MAX_BL1_RW_SIZE 0xA000 - -/* - * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a - * little space for growth. - */ -#if TRUSTED_BOARD_BOOT -# define PLAT_ARM_MAX_BL2_SIZE 0x1D000 -#else -# define PLAT_ARM_MAX_BL2_SIZE 0xC000 -#endif - -/* - * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a - * little space for growth. - */ -#define PLAT_ARM_MAX_BL31_SIZE 0x1D000 - #endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h index a2cf0368..c53e938f 100644 --- a/plat/arm/board/juno/include/platform_def.h +++ b/plat/arm/board/juno/include/platform_def.h @@ -74,10 +74,10 @@ #endif /* TRUSTED_BOARD_BOOT */ /* - * If ARM_BOARD_OPTIMISE_MMAP=0 then Juno uses the default, unoptimised values + * If ARM_BOARD_OPTIMISE_MEM=0 then Juno uses the default, unoptimised values * defined for ARM development platforms. */ -#if ARM_BOARD_OPTIMISE_MMAP +#if ARM_BOARD_OPTIMISE_MEM /* * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the * plat_arm_mmap array defined for each BL stage. @@ -107,7 +107,33 @@ # define MAX_XLAT_TABLES 3 #endif -#endif /* ARM_BOARD_OPTIMISE_MMAP */ +/* + * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size + * plus a little space for growth. + */ +#if TRUSTED_BOARD_BOOT +# define PLAT_ARM_MAX_BL1_RW_SIZE 0x9000 +#else +# define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000 +#endif + +/* + * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a + * little space for growth. + */ +#if TRUSTED_BOARD_BOOT +# define PLAT_ARM_MAX_BL2_SIZE 0x1D000 +#else +# define PLAT_ARM_MAX_BL2_SIZE 0xC000 +#endif + +/* + * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a + * little space for growth. + */ +#define PLAT_ARM_MAX_BL31_SIZE 0x1D000 + +#endif /* ARM_BOARD_OPTIMISE_MEM */ /* CCI related constants */ #define PLAT_ARM_CCI_BASE 0x2c090000 @@ -183,30 +209,4 @@ /* CSS SoC NIC-400 Global Programmers View (GPV) */ #define PLAT_SOC_CSS_NIC400_BASE 0x2a000000 -/* - * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size - * plus a little space for growth. - */ -#if TRUSTED_BOARD_BOOT -# define PLAT_ARM_MAX_BL1_RW_SIZE 0x9000 -#else -# define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000 -#endif - -/* - * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a - * little space for growth. - */ -#if TRUSTED_BOARD_BOOT -# define PLAT_ARM_MAX_BL2_SIZE 0x1D000 -#else -# define PLAT_ARM_MAX_BL2_SIZE 0xC000 -#endif - -/* - * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a - * little space for growth. - */ -#define PLAT_ARM_MAX_BL31_SIZE 0x1D000 - #endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk index 4fda4ca1..c1cfffc4 100644 --- a/plat/arm/board/juno/platform.mk +++ b/plat/arm/board/juno/platform.mk @@ -79,7 +79,7 @@ SKIP_A57_L1_FLUSH_PWR_DWN := 1 ENABLE_PLAT_COMPAT := 0 # Enable memory map related constants optimisation -ARM_BOARD_OPTIMISE_MMAP := 1 +ARM_BOARD_OPTIMISE_MEM := 1 include plat/arm/board/common/board_css.mk include plat/arm/common/arm_common.mk diff --git a/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S b/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S index 9f94b0c1..3378272c 100644 --- a/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S +++ b/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S @@ -70,7 +70,9 @@ sys_resume: psram_data: .quad PSRAM_DT_BASE sys_wakeup_entry: +#if !ERROR_DEPRECATED .quad psci_entrypoint +#endif pmu_cpuson_entrypoint_end: .word 0 endfunc pmu_cpuson_entrypoint diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c index e106211e..72d71bf7 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c @@ -747,9 +747,6 @@ static void sys_slp_config(void) BIT_WITH_WMSK(PMU_CLR_CORE_L_2GIC_HW) | BIT_WITH_WMSK(PMU_CLR_GIC2_CORE_L_HW)); - mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1A_IOMUX, - BIT_WITH_WMSK(AP_PWROFF)); - slp_mode_cfg = BIT(PMU_PWR_MODE_EN) | BIT(PMU_POWER_OFF_REQ_CFG) | BIT(PMU_CPU0_PD_EN) | @@ -778,18 +775,18 @@ static void sys_slp_config(void) mmio_setbits_32(PMU_BASE + PMU_WKUP_CFG4, BIT(PMU_GPIO_WKUP_EN)); mmio_write_32(PMU_BASE + PMU_PWRMODE_CON, slp_mode_cfg); - mmio_write_32(PMU_BASE + PMU_SCU_L_PWRDN_CNT, CYCL_32K_CNT_MS(5)); - mmio_write_32(PMU_BASE + PMU_SCU_L_PWRUP_CNT, CYCL_32K_CNT_MS(5)); - mmio_write_32(PMU_BASE + PMU_SCU_B_PWRDN_CNT, CYCL_32K_CNT_MS(5)); - mmio_write_32(PMU_BASE + PMU_SCU_B_PWRUP_CNT, CYCL_32K_CNT_MS(5)); - mmio_write_32(PMU_BASE + PMU_CENTER_PWRDN_CNT, CYCL_32K_CNT_MS(5)); - mmio_write_32(PMU_BASE + PMU_CENTER_PWRUP_CNT, CYCL_32K_CNT_MS(5)); - mmio_write_32(PMU_BASE + PMU_WAKEUP_RST_CLR_CNT, CYCL_32K_CNT_MS(5)); - mmio_write_32(PMU_BASE + PMU_OSC_CNT, CYCL_32K_CNT_MS(5)); - mmio_write_32(PMU_BASE + PMU_DDRIO_PWRON_CNT, CYCL_32K_CNT_MS(5)); - mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT, CYCL_32K_CNT_MS(5)); - mmio_write_32(PMU_BASE + PMU_PLLRST_CNT, CYCL_32K_CNT_MS(5)); - mmio_write_32(PMU_BASE + PMU_STABLE_CNT, CYCL_32K_CNT_MS(5)); + mmio_write_32(PMU_BASE + PMU_SCU_L_PWRDN_CNT, CYCL_24M_CNT_MS(3)); + mmio_write_32(PMU_BASE + PMU_SCU_L_PWRUP_CNT, CYCL_24M_CNT_MS(3)); + mmio_write_32(PMU_BASE + PMU_SCU_B_PWRDN_CNT, CYCL_24M_CNT_MS(3)); + mmio_write_32(PMU_BASE + PMU_SCU_B_PWRUP_CNT, CYCL_24M_CNT_MS(3)); + mmio_write_32(PMU_BASE + PMU_CENTER_PWRDN_CNT, CYCL_24M_CNT_MS(3)); + mmio_write_32(PMU_BASE + PMU_CENTER_PWRUP_CNT, CYCL_24M_CNT_MS(3)); + mmio_write_32(PMU_BASE + PMU_WAKEUP_RST_CLR_CNT, CYCL_24M_CNT_MS(3)); + mmio_write_32(PMU_BASE + PMU_OSC_CNT, CYCL_32K_CNT_MS(3)); + mmio_write_32(PMU_BASE + PMU_DDRIO_PWRON_CNT, CYCL_24M_CNT_MS(3)); + mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT, CYCL_24M_CNT_MS(3)); + mmio_write_32(PMU_BASE + PMU_PLLRST_CNT, CYCL_24M_CNT_MS(3)); + mmio_write_32(PMU_BASE + PMU_STABLE_CNT, CYCL_24M_CNT_MS(3)); mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(PMU_24M_EN_CFG)); mmio_write_32(PMU_BASE + PMU_PLL_CON, PLL_PD_HW); @@ -807,6 +804,72 @@ static void clr_hw_idle(uint32_t hw_idle) mmio_clrbits_32(PMU_BASE + PMU_BUS_CLR, hw_idle); } +struct pwm_data_s pwm_data; + +/* + * Save the PWMs data. + */ +static void save_pwms(void) +{ + uint32_t i; + + pwm_data.iomux_bitmask = 0; + + /* Save all IOMUXes */ + if (mmio_read_32(GRF_BASE + GRF_GPIO4C_IOMUX) & GPIO4C2_IOMUX_PWM) + pwm_data.iomux_bitmask |= PWM0_IOMUX_PWM_EN; + if (mmio_read_32(GRF_BASE + GRF_GPIO4C_IOMUX) & GPIO4C6_IOMUX_PWM) + pwm_data.iomux_bitmask |= PWM1_IOMUX_PWM_EN; + if (mmio_read_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX) & + GPIO1C3_IOMUX_PWM) + pwm_data.iomux_bitmask |= PWM2_IOMUX_PWM_EN; + if (mmio_read_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX) & + GPIO0A6_IOMUX_PWM) + pwm_data.iomux_bitmask |= PWM3_IOMUX_PWM_EN; + + for (i = 0; i < 4; i++) { + /* Save cnt, period, duty and ctrl for PWM i */ + pwm_data.cnt[i] = mmio_read_32(PWM_BASE + PWM_CNT(i)); + pwm_data.duty[i] = mmio_read_32(PWM_BASE + PWM_PERIOD_HPR(i)); + pwm_data.period[i] = mmio_read_32(PWM_BASE + PWM_DUTY_LPR(i)); + pwm_data.ctrl[i] = mmio_read_32(PWM_BASE + PWM_CTRL(i)); + } + + /* PWMs all IOMUXes switch to the gpio mode */ + mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, GPIO4C2_IOMUX_GPIO); + mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, GPIO4C6_IOMUX_GPIO); + mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX, GPIO1C3_IOMUX_GPIO); + mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, GPIO0A6_IOMUX_GPIO); +} + +/* + * Restore the PWMs data. + */ +static void restore_pwms(void) +{ + uint32_t i; + + /* Restore all IOMUXes */ + if (pwm_data.iomux_bitmask & PWM3_IOMUX_PWM_EN) + mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, + GPIO0A6_IOMUX_PWM); + if (pwm_data.iomux_bitmask & PWM2_IOMUX_PWM_EN) + mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX, + GPIO1C3_IOMUX_PWM); + if (pwm_data.iomux_bitmask & PWM1_IOMUX_PWM_EN) + mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, GPIO4C6_IOMUX_PWM); + if (pwm_data.iomux_bitmask & PWM0_IOMUX_PWM_EN) + mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, GPIO4C2_IOMUX_PWM); + + for (i = 0; i < 4; i++) { + /* Restore ctrl, duty, period and cnt for PWM i */ + mmio_write_32(PWM_BASE + PWM_CTRL(i), pwm_data.ctrl[i]); + mmio_write_32(PWM_BASE + PWM_DUTY_LPR(i), pwm_data.period[i]); + mmio_write_32(PWM_BASE + PWM_PERIOD_HPR(i), pwm_data.duty[i]); + mmio_write_32(PWM_BASE + PWM_CNT(i), pwm_data.cnt[i]); + } +} + static int sys_pwr_domain_suspend(void) { uint32_t wait_cnt = 0; @@ -853,8 +916,7 @@ static int sys_pwr_domain_suspend(void) } mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN)); - /* TODO: Wait SoC to cut off the logic_center, switch the gpio mode */ - mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, GPIO0A6_IOMUX_GPIO); + save_pwms(); return 0; } @@ -864,8 +926,7 @@ static int sys_pwr_domain_resume(void) uint32_t wait_cnt = 0; uint32_t status = 0; - /* TODO: switch the pwm mode */ - mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, GPIO0A6_IOMUX_PWM); + restore_pwms(); pmu_sgrf_rst_hld(); diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.h b/plat/rockchip/rk3399/drivers/pmu/pmu.h index 797282f1..ddb1c166 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu.h +++ b/plat/rockchip/rk3399/drivers/pmu/pmu.h @@ -810,10 +810,20 @@ enum pmu_core_pwr_st { #define PMUGRF_GPIO0A_IOMUX 0x00 #define PMUGRF_GPIO1A_IOMUX 0x10 +#define PMUGRF_GPIO1C_IOMUX 0x18 + #define AP_PWROFF 0x0a + #define GPIO0A6_IOMUX_GPIO BITS_WITH_WMASK(0, 3, 12) #define GPIO0A6_IOMUX_PWM BITS_WITH_WMASK(1, 3, 12) +#define GPIO1C3_IOMUX_GPIO BITS_WITH_WMASK(0, 3, 6) +#define GPIO1C3_IOMUX_PWM BITS_WITH_WMASK(1, 3, 6) +#define GPIO4C2_IOMUX_GPIO BITS_WITH_WMASK(0, 3, 4) +#define GPIO4C2_IOMUX_PWM BITS_WITH_WMASK(1, 3, 4) +#define GPIO4C6_IOMUX_GPIO BITS_WITH_WMASK(0, 3, 12) +#define GPIO4C6_IOMUX_PWM BITS_WITH_WMASK(1, 3, 12) #define GPIO1A6_IOMUX BITS_WITH_WMASK(0, 3, 12) + #define TSADC_INT_PIN 38 #define CORES_PM_DISABLE 0x0 #define CPU_AXI_QOS_ID_COREID 0x00 @@ -867,6 +877,8 @@ enum pmu_core_pwr_st { #define MAX_WAIT_COUNT 1000 #define GRF_SOC_CON4 0x0e210 +#define GRF_GPIO4C_IOMUX 0x0e028 + #define PMUGRF_SOC_CON0 0x0180 #define CCI_FORCE_WAKEUP WMSK_BIT(8) @@ -901,6 +913,15 @@ enum pmu_core_pwr_st { mmio_write_32(base + CPU_AXI_QOS_EXTCONTROL, array[6]); \ } while (0) +/* there are 4 PWMs on rk3399 */ +struct pwm_data_s { + uint32_t iomux_bitmask; + uint64_t cnt[4]; + uint64_t duty[4]; + uint64_t period[4]; + uint64_t ctrl[4]; +}; + struct pmu_slpdata_s { uint32_t cci_m0_qos[CPU_AXI_QOS_NUM_REGS]; uint32_t cci_m1_qos[CPU_AXI_QOS_NUM_REGS]; diff --git a/plat/rockchip/rk3399/drivers/soc/soc.c b/plat/rockchip/rk3399/drivers/soc/soc.c index d11a2f64..9ccf90c4 100644 --- a/plat/rockchip/rk3399/drivers/soc/soc.c +++ b/plat/rockchip/rk3399/drivers/soc/soc.c @@ -39,43 +39,7 @@ /* Table of regions to map using the MMU. */ const mmap_region_t plat_rk_mmap[] = { - MAP_REGION_FLAT(GIC500_BASE, GIC500_SIZE, - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(CCI500_BASE, CCI500_SIZE, - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(STIME_BASE, STIME_SIZE, - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(CRUS_BASE, CRUS_SIZE, - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE, - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(PMU_BASE, PMU_SIZE, - MT_DEVICE | MT_RW | MT_NS), - MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE, - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(RK3399_UART2_BASE, RK3399_UART2_SIZE, - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(PMUGRF_BASE, PMUGRF_SIZE, - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(GPIO0_BASE, GPIO0_SIZE, - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(GPIO1_BASE, GPIO1_SIZE, - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(GPIO2_BASE, GPIO2_SIZE, - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(GPIO3_BASE, GPIO3_SIZE, - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(GPIO4_BASE, GPIO4_SIZE, - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(GRF_BASE, GRF_SIZE, - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(SERVICE_NOC_0_BASE, NOC_0_SIZE, - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(SERVICE_NOC_1_BASE, NOC_1_SIZE, - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(SERVICE_NOC_2_BASE, NOC_2_SIZE, - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(SERVICE_NOC_3_BASE, NOC_3_SIZE, + MAP_REGION_FLAT(RK3399_DEV_RNG0_BASE, RK3399_DEV_RNG0_SIZE, MT_DEVICE | MT_RW | MT_SECURE), { 0 } diff --git a/plat/rockchip/rk3399/rk3399_def.h b/plat/rockchip/rk3399/rk3399_def.h index 162869e0..787ec0cb 100644 --- a/plat/rockchip/rk3399/rk3399_def.h +++ b/plat/rockchip/rk3399/rk3399_def.h @@ -39,72 +39,82 @@ #define SIZE_K(n) ((n) * 1024) #define SIZE_M(n) ((n) * 1024 * 1024) -#define CCI500_BASE 0xffb00000 -#define CCI500_SIZE SIZE_M(1) +/* Register base address and size */ +#define MMIO_BASE 0xfe000000 -#define GIC500_BASE 0xfee00000 +#define GIC500_BASE (MMIO_BASE + 0xe00000) #define GIC500_SIZE SIZE_M(2) -#define STIME_BASE 0xff860000 -#define STIME_SIZE SIZE_K(64) - -#define CRUS_BASE 0xff750000 -#define CRUS_SIZE SIZE_K(128) +#define PMU_BASE (MMIO_BASE + 0x1310000) +#define PMU_SIZE SIZE_K(64) -#define SGRF_BASE 0xff330000 -#define SGRF_SIZE SIZE_K(64) +#define PMUGRF_BASE (MMIO_BASE + 0x1320000) +#define PMUGRF_SIZE SIZE_K(64) -#define PMU_BASE 0xff310000 -#define PMU_SIZE SIZE_K(64) +#define SGRF_BASE (MMIO_BASE + 0x1330000) +#define SGRF_SIZE SIZE_K(64) -#define PMUSRAM_BASE 0xff3b0000 +#define PMUSRAM_BASE (MMIO_BASE + 0x13b0000) #define PMUSRAM_SIZE SIZE_K(64) #define PMUSRAM_RSIZE SIZE_K(8) -#define PMUGRF_BASE 0xff320000 -#define PMUGRF_SIZE SIZE_K(64) +#define PWM_BASE (MMIO_BASE + 0x1420000) +#define PWM_SIZE SIZE_K(64) -#define GPIO0_BASE 0xff720000 +#define GPIO0_BASE (MMIO_BASE + 0x1720000) #define GPIO0_SIZE SIZE_K(64) -#define GPIO1_BASE 0xff730000 +#define GPIO1_BASE (MMIO_BASE + 0x1730000) #define GPIO1_SIZE SIZE_K(64) -#define GPIO2_BASE 0xff780000 +#define CRUS_BASE (MMIO_BASE + 0x1750000) +#define CRUS_SIZE SIZE_K(128) + +#define GRF_BASE (MMIO_BASE + 0x1770000) +#define GRF_SIZE SIZE_K(64) + +#define GPIO2_BASE (MMIO_BASE + 0x1780000) #define GPIO2_SIZE SIZE_K(32) -#define GPIO3_BASE 0xff788000 +#define GPIO3_BASE (MMIO_BASE + 0x1788000) #define GPIO3_SIZE SIZE_K(32) -#define GPIO4_BASE 0xff790000 +#define GPIO4_BASE (MMIO_BASE + 0x1790000) #define GPIO4_SIZE SIZE_K(32) -#define GRF_BASE 0xff770000 -#define GRF_SIZE SIZE_K(64) +#define STIME_BASE (MMIO_BASE + 0x1860000) +#define STIME_SIZE SIZE_K(64) -#define SERVICE_NOC_0_BASE 0xffa50000 +#define SERVICE_NOC_0_BASE (MMIO_BASE + 0x1a50000) #define NOC_0_SIZE SIZE_K(192) -#define SERVICE_NOC_1_BASE 0xffa84000 +#define SERVICE_NOC_1_BASE (MMIO_BASE + 0x1a84000) #define NOC_1_SIZE SIZE_K(16) -#define SERVICE_NOC_2_BASE 0xffa8c000 +#define SERVICE_NOC_2_BASE (MMIO_BASE + 0x1a8c000) #define NOC_2_SIZE SIZE_K(16) -#define SERVICE_NOC_3_BASE 0xffa90000 +#define SERVICE_NOC_3_BASE (MMIO_BASE + 0x1a90000) #define NOC_3_SIZE SIZE_K(448) +#define CCI500_BASE (MMIO_BASE + 0x1b00000) +#define CCI500_SIZE SIZE_M(1) + +/* Aggregate of all devices in the first GB */ +#define RK3399_DEV_RNG0_BASE MMIO_BASE +#define RK3399_DEV_RNG0_SIZE 0x1d00000 + /* * include i2c pmu/audio, pwm0-3 rkpwm0-3 uart_dbg,mailbox scr * 0xff650000 -0xff6c0000 */ -#define PD_BUS0_BASE 0xff650000 -#define PD_BUS0_SIZE 0x70000 +#define PD_BUS0_BASE (MMIO_BASE + 0x1650000) +#define PD_BUS0_SIZE SIZE_K(448) -#define PMUCRU_BASE 0xff750000 -#define CRU_BASE 0xff760000 +#define PMUCRU_BASE (MMIO_BASE + 0x1750000) +#define CRU_BASE (MMIO_BASE + 0x1760000) -#define COLD_BOOT_BASE 0xffff0000 +#define COLD_BOOT_BASE (MMIO_BASE + 0x1ff0000) /************************************************************************** * UART related constants @@ -151,4 +161,14 @@ #define RK3399_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER #define RK3399_G0_IRQS ARM_IRQ_SEC_SGI_6 +#define PWM0_IOMUX_PWM_EN (1 << 0) +#define PWM1_IOMUX_PWM_EN (1 << 1) +#define PWM2_IOMUX_PWM_EN (1 << 2) +#define PWM3_IOMUX_PWM_EN (1 << 3) + +#define PWM_CNT(n) 0x0000 + 0x10 * n +#define PWM_PERIOD_HPR(n) 0x0004 + 0x10 * n +#define PWM_DUTY_LPR(n) 0x0008 + 0x10 * n +#define PWM_CTRL(n) 0x000c + 0x10 * n + #endif /* __PLAT_DEF_H__ */ |