diff options
| -rw-r--r-- | Makefile | 8 | ||||
| -rw-r--r-- | docs/cpu-specific-build-macros.md | 19 | ||||
| -rw-r--r-- | drivers/arm/ccn/ccn.c | 97 | ||||
| -rw-r--r-- | drivers/arm/ccn/ccn_private.h | 19 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a57.h | 7 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a35.S | 6 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a53.S | 39 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a57.S | 58 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cpu_helpers.S | 17 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk | 18 | ||||
| -rw-r--r-- | make_helpers/build_macros.mk | 6 | ||||
| -rw-r--r-- | services/std_svc/psci/psci_common.c | 1 |
12 files changed, 167 insertions, 128 deletions
@@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: @@ -294,9 +294,9 @@ ifneq (${ENABLE_PLAT_COMPAT}, 0) include plat/compat/plat_compat.mk endif -# Include the CPU specific operations makefile. By default all CPU errata -# workarounds and CPU specific optimisations are disabled. This can be -# overridden by the platform. +# Include the CPU specific operations makefile, which provides default +# values for all CPU errata workarounds and CPU specific optimisations. +# This can be overridden by the platform. include lib/cpus/cpu-ops.mk diff --git a/docs/cpu-specific-build-macros.md b/docs/cpu-specific-build-macros.md index d9b7108c..e7185aa4 100644 --- a/docs/cpu-specific-build-macros.md +++ b/docs/cpu-specific-build-macros.md @@ -26,8 +26,8 @@ by ARM. The errata workarounds are implemented for a particular revision or a set of processor revisions. This is checked by reset handler at runtime. Each errata workaround is identified by its `ID` as specified in the processor's errata notice document. The format of the define used to enable/disable the -errata is `ERRATA_<Processor name>_<ID>` where the `Processor name` -is either `A57` for the `Cortex_A57` CPU or `A53` for `Cortex_A53` CPU. +errata workaround is `ERRATA_<Processor name>_<ID>`, where the `Processor name` +is for example `A57` for the `Cortex_A57` CPU. All workarounds are disabled by default. The platform is reponsible for enabling these workarounds according to its requirement by defining the @@ -74,6 +74,19 @@ architecture that can be enabled by the platform as desired. sequence. Each Cortex-A57 based platform must make its own decision on whether to use the optimization. +* `A53_DISABLE_NON_TEMPORAL_HINT`: This flag disables the cache non-temporal + hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave + in a way most programmers expect, and will most probably result in a + significant speed degradation to any code that employs them. The ARMv8-A + architecture (see ARM DDI 0487A.h, section D3.4.3) allows cores to ignore + the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this + flag enforces this behaviour. This needs to be enabled only for revisions + <= r0p3 of the CPU and is enabled by default. + +* `A57_DISABLE_NON_TEMPORAL_HINT`: This flag has the same behaviour as + `A53_DISABLE_NON_TEMPORAL_HINT` but for Cortex-A57. This needs to be + enabled only for revisions <= r1p2 of the CPU and is enabled by default. + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -_Copyright (c) 2014, ARM Limited and Contributors. All rights reserved._ +_Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved._ diff --git a/drivers/arm/ccn/ccn.c b/drivers/arm/ccn/ccn.c index aef891b2..28d27098 100644 --- a/drivers/arm/ccn/ccn.c +++ b/drivers/arm/ccn/ccn.c @@ -268,7 +268,7 @@ static unsigned long long ccn_master_to_rn_id_map(unsigned long long master_map) /******************************************************************************* * This function executes the necessary operations to add or remove Request node * IDs specified in the 'rn_id_map' bitmap from the snoop/DVM domains specified - * in the 'hn_id_map'. The 'region_id' specifies the ID of the first HN-F/HN-I + * in the 'hn_id_map'. The 'region_id' specifies the ID of the first HN-F/MN * on which the operation should be performed. 'op_reg_offset' specifies the * type of operation (add/remove). 'stat_reg_offset' specifies the register * which should be polled to determine if the operation has completed or not. @@ -310,35 +310,6 @@ static void ccn_snoop_dvm_do_op(unsigned long long rn_id_map, } /******************************************************************************* - * This function reads the bitmap of Home nodes on the basis of the - * 'mn_hn_id_reg_offset' parameter from the Miscellaneous node's (MN) - * programmer's view. The MN has a register which carries the bitmap of present - * Home nodes of each type i.e. HN-Fs, HN-Is & HN-Ds. It calls - * 'ccn_snoop_dvm_do_op()' with this information to perform the actual - * operation. - ******************************************************************************/ -static void ccn_snoop_dvm_domain_common(unsigned long long rn_id_map, - unsigned int hn_op_reg_offset, - unsigned int hn_stat_reg_offset, - unsigned int mn_hn_id_reg_offset, - unsigned int hn_region_id) -{ - unsigned long long mn_hn_id_map; - - assert(ccn_plat_desc); - assert(ccn_plat_desc->periphbase); - - mn_hn_id_map = ccn_reg_read(ccn_plat_desc->periphbase, - MN_REGION_ID, - mn_hn_id_reg_offset); - ccn_snoop_dvm_do_op(rn_id_map, - mn_hn_id_map, - hn_region_id, - hn_op_reg_offset, - hn_stat_reg_offset); -} - -/******************************************************************************* * The following functions provide the boot and runtime API to the platform for * adding and removing master interfaces from the snoop/DVM domains. A bitmap of * master interfaces IDs is passed as a parameter. It is converted into a bitmap @@ -357,17 +328,18 @@ void ccn_enter_snoop_dvm_domain(unsigned long long master_iface_map) unsigned long long rn_id_map; rn_id_map = ccn_master_to_rn_id_map(master_iface_map); - ccn_snoop_dvm_domain_common(rn_id_map, - HNF_SDC_SET_OFFSET, - HNF_SDC_STAT_OFFSET, - MN_HNF_NODEID_OFFSET, - HNF_REGION_ID_START); - - ccn_snoop_dvm_domain_common(rn_id_map, - MN_DDC_SET_OFF, - MN_DDC_STAT_OFFSET, - MN_HNI_NODEID_OFFSET, - MN_REGION_ID); + ccn_snoop_dvm_do_op(rn_id_map, + CCN_GET_HN_NODEID_MAP(ccn_plat_desc->periphbase, + MN_HNF_NODEID_OFFSET), + HNF_REGION_ID_START, + HNF_SDC_SET_OFFSET, + HNF_SDC_STAT_OFFSET); + + ccn_snoop_dvm_do_op(rn_id_map, + CCN_GET_MN_NODEID_MAP(ccn_plat_desc->periphbase), + MN_REGION_ID, + MN_DDC_SET_OFFSET, + MN_DDC_STAT_OFFSET); } void ccn_exit_snoop_dvm_domain(unsigned long long master_iface_map) @@ -375,17 +347,18 @@ void ccn_exit_snoop_dvm_domain(unsigned long long master_iface_map) unsigned long long rn_id_map; rn_id_map = ccn_master_to_rn_id_map(master_iface_map); - ccn_snoop_dvm_domain_common(rn_id_map, - HNF_SDC_CLR_OFFSET, - HNF_SDC_STAT_OFFSET, - MN_HNF_NODEID_OFFSET, - HNF_REGION_ID_START); - - ccn_snoop_dvm_domain_common(rn_id_map, - MN_DDC_CLR_OFFSET, - MN_DDC_STAT_OFFSET, - MN_HNI_NODEID_OFFSET, - MN_REGION_ID); + ccn_snoop_dvm_do_op(rn_id_map, + CCN_GET_HN_NODEID_MAP(ccn_plat_desc->periphbase, + MN_HNF_NODEID_OFFSET), + HNF_REGION_ID_START, + HNF_SDC_CLR_OFFSET, + HNF_SDC_STAT_OFFSET); + + ccn_snoop_dvm_do_op(rn_id_map, + CCN_GET_MN_NODEID_MAP(ccn_plat_desc->periphbase), + MN_REGION_ID, + MN_DDC_CLR_OFFSET, + MN_DDC_STAT_OFFSET); } void ccn_enter_dvm_domain(unsigned long long master_iface_map) @@ -393,11 +366,11 @@ void ccn_enter_dvm_domain(unsigned long long master_iface_map) unsigned long long rn_id_map; rn_id_map = ccn_master_to_rn_id_map(master_iface_map); - ccn_snoop_dvm_domain_common(rn_id_map, - MN_DDC_SET_OFF, - MN_DDC_STAT_OFFSET, - MN_HNI_NODEID_OFFSET, - MN_REGION_ID); + ccn_snoop_dvm_do_op(rn_id_map, + CCN_GET_MN_NODEID_MAP(ccn_plat_desc->periphbase), + MN_REGION_ID, + MN_DDC_SET_OFFSET, + MN_DDC_STAT_OFFSET); } void ccn_exit_dvm_domain(unsigned long long master_iface_map) @@ -405,11 +378,11 @@ void ccn_exit_dvm_domain(unsigned long long master_iface_map) unsigned long long rn_id_map; rn_id_map = ccn_master_to_rn_id_map(master_iface_map); - ccn_snoop_dvm_domain_common(rn_id_map, - MN_DDC_CLR_OFFSET, - MN_DDC_STAT_OFFSET, - MN_HNI_NODEID_OFFSET, - MN_REGION_ID); + ccn_snoop_dvm_do_op(rn_id_map, + CCN_GET_MN_NODEID_MAP(ccn_plat_desc->periphbase), + MN_REGION_ID, + MN_DDC_CLR_OFFSET, + MN_DDC_STAT_OFFSET); } /******************************************************************************* diff --git a/drivers/arm/ccn/ccn_private.h b/drivers/arm/ccn/ccn_private.h index e92e8702..8b154725 100644 --- a/drivers/arm/ccn/ccn_private.h +++ b/drivers/arm/ccn/ccn_private.h @@ -147,7 +147,7 @@ typedef enum rn_types { #define MN_HNI_NODEID_OFFSET 0x01C0 #define MN_SN_NODEID_OFFSET 0x01D0 #define MN_DDC_STAT_OFFSET DOMAIN_CTRL_STAT_OFFSET -#define MN_DDC_SET_OFF DOMAIN_CTRL_SET_OFFSET +#define MN_DDC_SET_OFFSET DOMAIN_CTRL_SET_OFFSET #define MN_DDC_CLR_OFFSET DOMAIN_CTRL_CLR_OFFSET #define MN_ID_OFFSET REGION_ID_OFFSET @@ -236,4 +236,21 @@ static inline unsigned int count_set_bits(uint64_t bitmap) */ #define FOR_EACH_PRESENT_MASTER_INTERFACE(iface_id, bit_map) \ FOR_EACH_BIT(iface_id, bit_map) + +/* + * Macro that returns the node id bit map for the Miscellaneous Node + */ +#define CCN_GET_MN_NODEID_MAP(periphbase) \ + (1 << get_node_id(ccn_reg_read(periphbase, MN_REGION_ID, \ + REGION_ID_OFFSET))) + +/* + * This macro returns the bitmap of Home nodes on the basis of the + * 'mn_hn_id_reg_offset' parameter from the Miscellaneous node's (MN) + * programmer's view. The MN has a register which carries the bitmap of present + * Home nodes of each type i.e. HN-Fs, HN-Is & HN-Ds. + */ +#define CCN_GET_HN_NODEID_MAP(periphbase, mn_hn_id_reg_offset) \ + ccn_reg_read(periphbase, MN_REGION_ID, mn_hn_id_reg_offset) + #endif /* __CCN_PRIVATE_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index c81259c8..c512129a 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -61,8 +61,9 @@ ******************************************************************************/ #define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ -#define CPUACTLR_NO_ALLOC_WBWA (1 << 49) -#define CPUACTLR_DCC_AS_DCCI (1 << 44) +#define CPUACTLR_DIS_OVERREAD (1 << 52) +#define CPUACTLR_NO_ALLOC_WBWA (1 << 49) +#define CPUACTLR_DCC_AS_DCCI (1 << 44) /******************************************************************************* * L2 Control register specific definitions. diff --git a/lib/cpus/aarch64/cortex_a35.S b/lib/cpus/aarch64/cortex_a35.S index 6a447c01..ba29d6d4 100644 --- a/lib/cpus/aarch64/cortex_a35.S +++ b/lib/cpus/aarch64/cortex_a35.S @@ -67,16 +67,12 @@ endfunc cortex_a35_disable_smp */ func cortex_a35_reset_func /* --------------------------------------------- - * As a bare minimum enable the SMP bit if it is - * not already set. + * Enable the SMP bit. * --------------------------------------------- */ mrs x0, CORTEX_A35_CPUECTLR_EL1 - tst x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT - b.ne skip_smp_setup orr x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT msr CORTEX_A35_CPUECTLR_EL1, x0 -skip_smp_setup: isb ret endfunc cortex_a35_reset_func diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S index e4b94e80..c33ba571 100644 --- a/lib/cpus/aarch64/cortex_a53.S +++ b/lib/cpus/aarch64/cortex_a53.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -86,33 +86,40 @@ apply_826319: ret endfunc errata_a53_826319_wa - /* -------------------------------------------------- - * Errata Workaround for Cortex A53 Errata #836870. - * This applies only to revision <= r0p3 of Cortex A53. - * From r0p4 and onwards, this errata is enabled by - * default. + /* --------------------------------------------------------------------- + * Disable the cache non-temporal hint. + * + * This ignores the Transient allocation hint in the MAIR and treats + * allocations the same as non-transient allocation types. As a result, + * the LDNP and STNP instructions in AArch64 behave the same as the + * equivalent LDP and STP instructions. + * + * This is relevant only for revisions <= r0p3 of Cortex-A53. + * From r0p4 and onwards, the bit to disable the hint is enabled by + * default at reset. + * * Inputs: * x0: variant[4:7] and revision[0:3] of current cpu. * Clobbers : x0 - x5 - * -------------------------------------------------- + * --------------------------------------------------------------------- */ -func errata_a53_836870_wa +func a53_disable_non_temporal_hint /* * Compare x0 against revision r0p3 */ cmp x0, #3 - b.ls apply_836870 + b.ls disable_hint #if DEBUG b print_revision_warning #else ret #endif -apply_836870: +disable_hint: mrs x1, CPUACTLR_EL1 orr x1, x1, #CPUACTLR_DTAH msr CPUACTLR_EL1, x1 ret -endfunc errata_a53_836870_wa +endfunc a53_disable_non_temporal_hint /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A53. @@ -138,22 +145,18 @@ func cortex_a53_reset_func bl errata_a53_826319_wa #endif -#if ERRATA_A53_836870 +#if ERRATA_A53_836870 || A53_DISABLE_NON_TEMPORAL_HINT mov x0, x15 - bl errata_a53_836870_wa + bl a53_disable_non_temporal_hint #endif /* --------------------------------------------- - * As a bare minimum enable the SMP bit if it is - * not already set. + * Enable the SMP bit. * --------------------------------------------- */ mrs x0, CPUECTLR_EL1 - tst x0, #CPUECTLR_SMP_BIT - b.ne skip_smp_setup orr x0, x0, #CPUECTLR_SMP_BIT msr CPUECTLR_EL1, x0 -skip_smp_setup: isb ret x19 endfunc cortex_a53_reset_func diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index 05799d61..99db25b8 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -105,17 +105,9 @@ func errata_a57_806969_wa ret #endif apply_806969: - /* - * Test if errata has already been applied in an earlier - * invocation of the reset handler and does not need to - * be applied again. - */ mrs x1, CPUACTLR_EL1 - tst x1, #CPUACTLR_NO_ALLOC_WBWA - b.ne skip_806969 orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA msr CPUACTLR_EL1, x1 -skip_806969: ret endfunc errata_a57_806969_wa @@ -139,20 +131,41 @@ func errata_a57_813420_wa ret #endif apply_813420: - /* - * Test if errata has already been applied in an earlier - * invocation of the reset handler and does not need to - * be applied again. - */ mrs x1, CPUACTLR_EL1 - tst x1, #CPUACTLR_DCC_AS_DCCI - b.ne skip_813420 orr x1, x1, #CPUACTLR_DCC_AS_DCCI msr CPUACTLR_EL1, x1 -skip_813420: ret endfunc errata_a57_813420_wa + /* -------------------------------------------------------------------- + * Disable the over-read from the LDNP instruction. + * + * This applies to all revisions <= r1p2. The performance degradation + * observed with LDNP/STNP has been fixed on r1p3 and onwards. + * + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5, x30 + * --------------------------------------------------------------------- + */ +func a57_disable_ldnp_overread + /* + * Compare x0 against revision r1p2 + */ + cmp x0, #0x12 + b.ls disable_hint +#if DEBUG + b print_revision_warning +#else + ret +#endif +disable_hint: + mrs x1, CPUACTLR_EL1 + orr x1, x1, #CPUACTLR_DIS_OVERREAD + msr CPUACTLR_EL1, x1 + ret +endfunc a57_disable_ldnp_overread + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A57. * Clobbers: x0-x5, x15, x19, x30 @@ -181,17 +194,18 @@ func cortex_a57_reset_func bl errata_a57_813420_wa #endif +#if A57_DISABLE_NON_TEMPORAL_HINT + mov x0, x15 + bl a57_disable_ldnp_overread +#endif + /* --------------------------------------------- - * As a bare minimum enable the SMP bit if it is - * not already set. + * Enable the SMP bit. * --------------------------------------------- */ mrs x0, CPUECTLR_EL1 - tst x0, #CPUECTLR_SMP_BIT - b.ne skip_smp_setup orr x0, x0, #CPUECTLR_SMP_BIT msr CPUECTLR_EL1, x0 -skip_smp_setup: isb ret x19 endfunc cortex_a57_reset_func diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S index e8a13929..e41d95ba 100644 --- a/lib/cpus/aarch64/cpu_helpers.S +++ b/lib/cpus/aarch64/cpu_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -205,16 +205,17 @@ error_exit: endfunc get_cpu_ops_ptr #if DEBUG - /* - * This function prints a warning message to the crash console - * if the CPU revision/part number does not match the errata - * workaround enabled in the build. - * Clobber: x30, x0 - x5 - */ .section .rodata.rev_warn_str, "aS" rev_warn_str: - .asciz "Warning: Skipping Errata workaround for non matching CPU revision number.\n" + .asciz "Warning: Skipping CPU specific reset operation for non-matching CPU revision number.\n" + /* + * This function prints the above warning message to the crash console. + * It should be called when a CPU specific operation is enabled in the + * build but doesn't apply to this CPU revision/part number. + * + * Clobber: x30, x0 - x5 + */ .globl print_revision_warning func print_revision_warning mov x5, x30 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index a872360e..a3a08e15 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: @@ -32,10 +32,26 @@ # cluster is powered down. SKIP_A57_L1_FLUSH_PWR_DWN ?=0 +# Flag to disable the cache non-temporal hint. +# It is enabled by default. +A53_DISABLE_NON_TEMPORAL_HINT ?=1 + +# Flag to disable the cache non-temporal hint. +# It is enabled by default. +A57_DISABLE_NON_TEMPORAL_HINT ?=1 + # Process SKIP_A57_L1_FLUSH_PWR_DWN flag $(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN)) $(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN)) +# Process A53_DISABLE_NON_TEMPORAL_HINT flag +$(eval $(call assert_boolean,A53_DISABLE_NON_TEMPORAL_HINT)) +$(eval $(call add_define,A53_DISABLE_NON_TEMPORAL_HINT)) + +# Process A57_DISABLE_NON_TEMPORAL_HINT flag +$(eval $(call assert_boolean,A57_DISABLE_NON_TEMPORAL_HINT)) +$(eval $(call add_define,A57_DISABLE_NON_TEMPORAL_HINT)) + # CPU Errata Build flags. These should be enabled by the # platform if the errata needs to be applied. diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk index d6a4e3ab..b22eaf90 100644 --- a/make_helpers/build_macros.mk +++ b/make_helpers/build_macros.mk @@ -290,6 +290,10 @@ define MAKE_TOOL_ARGS $(if $(3),$(eval $(call FIP_ADD_PAYLOAD,$(2),--$(3),bl$(1)))) endef +# Allow overriding the timestamp, for example for reproducible builds, or to +# synchronize timestamps across multiple projects. +# This must be set to a C string (including quotes where applicable). +BUILD_MESSAGE_TIMESTAMP ?= __TIME__", "__DATE__ # MAKE_BL macro defines the targets and options to build each BL image. # Arguments: @@ -315,7 +319,7 @@ $(BUILD_DIR): $(ELF): $(OBJS) $(LINKERFILE) @echo " LD $$@" - @echo 'const char build_message[] = "Built : "__TIME__", "__DATE__; \ + @echo 'const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP); \ const char version_string[] = "${VERSION_STRING}";' | \ $$(CC) $$(CFLAGS) -xc - -o $(BUILD_DIR)/build_message.o $$(Q)$$(LD) -o $$@ $$(LDFLAGS) -Map=$(MAPFILE) --script $(LINKERFILE) \ diff --git a/services/std_svc/psci/psci_common.c b/services/std_svc/psci/psci_common.c index 465c5fd9..8a2b81c3 100644 --- a/services/std_svc/psci/psci_common.c +++ b/services/std_svc/psci/psci_common.c @@ -393,6 +393,7 @@ void psci_do_state_coordination(unsigned int end_pwrlvl, unsigned int start_idx, ncpus; plat_local_state_t target_state, *req_states; + assert(end_pwrlvl <= PLAT_MAX_PWR_LVL); parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; /* For level 0, the requested state will be equivalent |