diff options
| -rw-r--r-- | Makefile | 1 | ||||
| -rw-r--r-- | docs/porting-guide.md | 12 | ||||
| -rw-r--r-- | include/lib/aarch64/arch_helpers.h | 9 | ||||
| -rw-r--r-- | lib/aarch64/xlat_helpers.c | 127 | ||||
| -rw-r--r-- | plat/mediatek/mt8173/bl31_plat_setup.c | 18 | ||||
| -rw-r--r-- | plat/mediatek/mt8173/drivers/spm/spm.c | 4 | ||||
| -rw-r--r-- | plat/mediatek/mt8173/include/mt8173_def.h | 10 |
7 files changed, 34 insertions, 147 deletions
@@ -196,7 +196,6 @@ BL_COMMON_SOURCES += common/bl_common.c \ common/aarch64/debug.S \ lib/aarch64/cache_helpers.S \ lib/aarch64/misc_helpers.S \ - lib/aarch64/xlat_helpers.c \ lib/stdlib/abort.c \ lib/stdlib/assert.c \ lib/stdlib/exit.c \ diff --git a/docs/porting-guide.md b/docs/porting-guide.md index f1f14a8a..f8d0ff38 100644 --- a/docs/porting-guide.md +++ b/docs/porting-guide.md @@ -76,12 +76,12 @@ either mandatory or optional. A platform port must enable the Memory Management Unit (MMU) as well as the instruction and data caches for each BL stage. Setting up the translation tables is the responsibility of the platform port because memory maps differ -across platforms. A memory translation library (see `lib/aarch64/xlat_helpers.c` -and `lib/aarch64/xlat_tables.c`) is provided to help in this setup. Note that -although this library supports non-identity mappings, this is intended only for -re-mapping peripheral physical addresses and allows platforms with high I/O -addresses to reduce their virtual address space. All other addresses -corresponding to code and data must currently use an identity mapping. +across platforms. A memory translation library (see `lib/aarch64/xlat_tables.c`) +is provided to help in this setup. Note that although this library supports +non-identity mappings, this is intended only for re-mapping peripheral physical +addresses and allows platforms with high I/O addresses to reduce their virtual +address space. All other addresses corresponding to code and data must currently +use an identity mapping. In ARM standard platforms, each BL stage configures the MMU in the platform-specific architecture setup function, `blX_plat_arch_setup()`, and uses diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h index 6118c6eb..f9f0715f 100644 --- a/include/lib/aarch64/arch_helpers.h +++ b/include/lib/aarch64/arch_helpers.h @@ -113,15 +113,6 @@ static inline void _op ## _type(uint64_t v) \ } /******************************************************************************* - * Aarch64 translation tables manipulation helper prototypes -******************************************************************************/ -uint64_t create_table_desc(uint64_t *next_table_ptr); -uint64_t create_block_desc(uint64_t desc, uint64_t addr, uint32_t level); -uint64_t create_device_block(uint64_t output_addr, uint32_t level, uint32_t ns); -uint64_t create_romem_block(uint64_t output_addr, uint32_t level, uint32_t ns); -uint64_t create_rwmem_block(uint64_t output_addr, uint32_t level, uint32_t ns); - -/******************************************************************************* * TLB maintenance accessor prototypes ******************************************************************************/ DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) diff --git a/lib/aarch64/xlat_helpers.c b/lib/aarch64/xlat_helpers.c deleted file mode 100644 index d401ffc4..00000000 --- a/lib/aarch64/xlat_helpers.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <arch.h> -#include <assert.h> - -/******************************************************************************* - * Helper to create a level 1/2 table descriptor which points to a level 2/3 - * table. - ******************************************************************************/ -unsigned long create_table_desc(unsigned long *next_table_ptr) -{ - unsigned long desc = (unsigned long) next_table_ptr; - - /* Clear the last 12 bits */ - desc >>= FOUR_KB_SHIFT; - desc <<= FOUR_KB_SHIFT; - - desc |= TABLE_DESC; - - return desc; -} - -/******************************************************************************* - * Helper to create a level 1/2/3 block descriptor which maps the va to addr - ******************************************************************************/ -unsigned long create_block_desc(unsigned long desc, - unsigned long addr, - unsigned int level) -{ - switch (level) { - case LEVEL1: - desc |= (addr << FIRST_LEVEL_DESC_N) | BLOCK_DESC; - break; - case LEVEL2: - desc |= (addr << SECOND_LEVEL_DESC_N) | BLOCK_DESC; - break; - case LEVEL3: - desc |= (addr << THIRD_LEVEL_DESC_N) | TABLE_DESC; - break; - default: - assert(0); - } - - return desc; -} - -/******************************************************************************* - * Helper to create a level 1/2/3 block descriptor which maps the va to output_ - * addr with Device nGnRE attributes. - ******************************************************************************/ -unsigned long create_device_block(unsigned long output_addr, - unsigned int level, - unsigned int ns) -{ - unsigned long upper_attrs, lower_attrs, desc; - - lower_attrs = LOWER_ATTRS(ACCESS_FLAG | OSH | AP_RW); - lower_attrs |= LOWER_ATTRS(ns | ATTR_DEVICE_INDEX); - upper_attrs = UPPER_ATTRS(XN); - desc = upper_attrs | lower_attrs; - - return create_block_desc(desc, output_addr, level); -} - -/******************************************************************************* - * Helper to create a level 1/2/3 block descriptor which maps the va to output_ - * addr with inner-shareable normal wbwa read-only memory attributes. - ******************************************************************************/ -unsigned long create_romem_block(unsigned long output_addr, - unsigned int level, - unsigned int ns) -{ - unsigned long upper_attrs, lower_attrs, desc; - - lower_attrs = LOWER_ATTRS(ACCESS_FLAG | ISH | AP_RO); - lower_attrs |= LOWER_ATTRS(ns | ATTR_IWBWA_OWBWA_NTR_INDEX); - upper_attrs = UPPER_ATTRS(0ull); - desc = upper_attrs | lower_attrs; - - return create_block_desc(desc, output_addr, level); -} - -/******************************************************************************* - * Helper to create a level 1/2/3 block descriptor which maps the va to output_ - * addr with inner-shareable normal wbwa read-write memory attributes. - ******************************************************************************/ -unsigned long create_rwmem_block(unsigned long output_addr, - unsigned int level, - unsigned int ns) -{ - unsigned long upper_attrs, lower_attrs, desc; - - lower_attrs = LOWER_ATTRS(ACCESS_FLAG | ISH | AP_RW); - lower_attrs |= LOWER_ATTRS(ns | ATTR_IWBWA_OWBWA_NTR_INDEX); - upper_attrs = UPPER_ATTRS(XN); - desc = upper_attrs | lower_attrs; - - return create_block_desc(desc, output_addr, level); -} diff --git a/plat/mediatek/mt8173/bl31_plat_setup.c b/plat/mediatek/mt8173/bl31_plat_setup.c index 87837759..749009ea 100644 --- a/plat/mediatek/mt8173/bl31_plat_setup.c +++ b/plat/mediatek/mt8173/bl31_plat_setup.c @@ -50,13 +50,15 @@ unsigned long __COHERENT_RAM_START__; unsigned long __COHERENT_RAM_END__; /* - * The next 2 constants identify the extents of the code & RO data region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. + * The next 3 constants identify the extents of the code, RO data region and the + * limit of the BL31 image. These addresses are used by the MMU setup code and + * therefore they must be page-aligned. It is the responsibility of the linker + * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols + * refer to page-aligned addresses. */ #define BL31_RO_BASE (unsigned long)(&__RO_START__) #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) +#define BL31_END (unsigned long)(&__BL31_END__) /* * The next 2 constants identify the extents of the coherent memory region. @@ -108,6 +110,13 @@ static void platform_setup_cpu(void) MCU_BUS_DCM_EN); } +static void platform_setup_sram(void) +{ + /* protect BL31 memory from non-secure read/write access */ + mmio_write_32(SRAMROM_SEC_ADDR, (uint32_t)(BL31_END + 0x3ff) & 0x3fc00); + mmio_write_32(SRAMROM_SEC_CTRL, 0x10000ff9); +} + /******************************************************************************* * Return a pointer to the 'entry_point_info' structure of the next image for * the security state specified. BL33 corresponds to the non-secure image type @@ -156,6 +165,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, void bl31_platform_setup(void) { platform_setup_cpu(); + platform_setup_sram(); plat_delay_timer_init(); diff --git a/plat/mediatek/mt8173/drivers/spm/spm.c b/plat/mediatek/mt8173/drivers/spm/spm.c index 45defd8a..f28b2640 100644 --- a/plat/mediatek/mt8173/drivers/spm/spm.c +++ b/plat/mediatek/mt8173/drivers/spm/spm.c @@ -384,6 +384,10 @@ enum wake_reason_t spm_output_wake_reason(struct wake_status *wakesta) void spm_boot_init(void) { + /* set spm transaction to secure mode */ + mmio_write_32(DEVAPC0_APC_CON, 0x0); + mmio_write_32(DEVAPC0_MAS_SEC_0, 0x200); + /* Only CPU0 is online during boot, initialize cpu online reserve bit */ mmio_write_32(SPM_PCM_RESERVE, 0xFE); mmio_clrbits_32(AP_PLL_CON3, 0xFFFFF); diff --git a/plat/mediatek/mt8173/include/mt8173_def.h b/plat/mediatek/mt8173/include/mt8173_def.h index 39bab149..0113d609 100644 --- a/plat/mediatek/mt8173/include/mt8173_def.h +++ b/plat/mediatek/mt8173/include/mt8173_def.h @@ -40,11 +40,13 @@ /* Register base address */ #define IO_PHYS (0x10000000) #define INFRACFG_AO_BASE (IO_PHYS + 0x1000) +#define SRAMROM_SEC_BASE (IO_PHYS + 0x1800) #define PERI_CON_BASE (IO_PHYS + 0x3000) #define GPIO_BASE (IO_PHYS + 0x5000) #define SPM_BASE (IO_PHYS + 0x6000) #define RGU_BASE (IO_PHYS + 0x7000) #define PMIC_WRAP_BASE (IO_PHYS + 0xD000) +#define DEVAPC0_BASE (IO_PHYS + 0xE000) #define MCUCFG_BASE (IO_PHYS + 0x200000) #define APMIXED_BASE (IO_PHYS + 0x209000) #define TRNG_BASE (IO_PHYS + 0x20F000) @@ -57,6 +59,14 @@ #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000) #define MTK_DEV_RNG1_SIZE 0x4000000 +/* SRAMROM related registers */ +#define SRAMROM_SEC_CTRL (SRAMROM_SEC_BASE + 0x4) +#define SRAMROM_SEC_ADDR (SRAMROM_SEC_BASE + 0x8) + +/* DEVAPC0 related registers */ +#define DEVAPC0_MAS_SEC_0 (DEVAPC0_BASE + 0x500) +#define DEVAPC0_APC_CON (DEVAPC0_BASE + 0xF00) + /******************************************************************************* * UART related constants ******************************************************************************/ |