diff options
| -rw-r--r-- | docs/firmware-design.md | 24 | ||||
| -rw-r--r-- | docs/firmware-update.md | 20 | ||||
| -rw-r--r-- | docs/interrupt-framework-design.md | 2 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a35.h | 44 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a35.S | 164 | ||||
| -rw-r--r-- | plat/arm/board/fvp/platform.mk | 4 |
6 files changed, 234 insertions, 24 deletions
diff --git a/docs/firmware-design.md b/docs/firmware-design.md index 5b6923ae..7ae1de32 100644 --- a/docs/firmware-design.md +++ b/docs/firmware-design.md @@ -8,7 +8,7 @@ Contents : 3. [EL3 runtime services framework](#3--el3-runtime-services-framework) 4. [Power State Coordination Interface](#4--power-state-coordination-interface) 5. [Secure-EL1 Payloads and Dispatchers](#5--secure-el1-payloads-and-dispatchers) -6. [Crash Reporting in BL31](#6--crash-reporting-in-bl3-1) +6. [Crash Reporting in BL31](#6--crash-reporting-in-bl31) 7. [Guidelines for Reset Handlers](#7--guidelines-for-reset-handlers) 8. [CPU specific operations framework](#8--cpu-specific-operations-framework) 9. [Memory layout of BL images](#9-memory-layout-of-bl-images) @@ -988,11 +988,11 @@ needs to be exported for each type of CPU in the platform. It is defined in `reset_func()`, `core_pwr_dwn()`, `cluster_pwr_dwn()` and `cpu_reg_dump()`. The CPU specific files in `lib/cpus` export a `cpu_ops` data structure with -suitable handlers for that CPU. For example, `lib/cpus/cortex_a53.S` exports -the `cpu_ops` for Cortex-A53 CPU. According to the platform configuration, -these CPU specific files must must be included in the build by the platform -makefile. The generic CPU specific operations framework code exists in -`lib/cpus/aarch64/cpu_helpers.S`. +suitable handlers for that CPU. For example, `lib/cpus/aarch64/cortex_a53.S` +exports the `cpu_ops` for Cortex-A53 CPU. According to the platform +configuration, these CPU specific files must be included in the build by +the platform makefile. The generic CPU specific operations framework code exists +in `lib/cpus/aarch64/cpu_helpers.S`. ### CPU specific Reset Handling @@ -1020,12 +1020,12 @@ entry is stored in per-CPU data by `init_cpu_ops()` so that it can be quickly retrieved during power down sequences. The PSCI service, upon receiving a power down request, determines the highest -affinity level at which to execute power down sequence for a particular CPU and +power level at which to execute power down sequence for a particular CPU and invokes the corresponding 'prepare' power down handler in the CPU specific -operations framework. For example, when a CPU executes a power down for affinity +operations framework. For example, when a CPU executes a power down for power level 0, the `prepare_core_pwr_dwn()` retrieves the `cpu_ops` pointer from the per-CPU data and the corresponding `core_pwr_dwn()` is invoked. Similarly when -a CPU executes power down at affinity level 1, the `prepare_cluster_pwr_dwn()` +a CPU executes power down at power level 1, the `prepare_cluster_pwr_dwn()` retrieves the `cpu_ops` pointer and the corresponding `cluster_pwr_dwn()` is invoked. @@ -1454,8 +1454,8 @@ The ARM development platforms' policy is to only allow loading of a known set of images. The platform policy can be modified to allow additional images. -11. Use of coherent memory in Trusted Firmware ----------------------------------------------- +11. Use of coherent memory in Trusted Firmware +----------------------------------------------- There might be loss of coherency when physical memory with mismatched shareability, cacheability and memory attributes is accessed by multiple CPUs @@ -1739,5 +1739,5 @@ _Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved._ [Porting Guide]: ./porting-guide.md [Reset Design]: ./reset-design.md [INTRG]: ./interrupt-framework-design.md -[CPUBM]: ./cpu-specific-build-macros.md.md +[CPUBM]: ./cpu-specific-build-macros.md [Firmware Update]: ./firmware-update.md diff --git a/docs/firmware-update.md b/docs/firmware-update.md index 419ac85c..97df8cf4 100644 --- a/docs/firmware-update.md +++ b/docs/firmware-update.md @@ -3,11 +3,11 @@ ARM Trusted Firmware - Firmware Update Design Guide Contents : -1. [Introduction](#1-introduction) -2. [FWU Overview](#2-fwu-overview) -3. [Image Identification](#3-image-identification) -4. [FWU State Machine](#4-fwu-state-machine) -5. [SMC Interface](#5-smc-interface) +1. [Introduction](#1--introduction) +2. [FWU Overview](#2--fwu-overview) +3. [Image Identification](#3--image-identification) +4. [FWU State Machine](#4--fwu-state-machine) +5. [BL1 SMC Interface](#5--bl1-smc-interface) - - - - - - - - - - - - - - - - - - @@ -35,8 +35,8 @@ FWU images, please refer to the "Non-Trusted Firmware Updater" requirements in the TBBR. -2. FWU Overview ---------------- +2. FWU Overview +---------------- The FWU boot flow is primarily mediated by BL1. Since BL1 executes in ROM, and it is usually desirable to minimize the amount of ROM code, the design allows @@ -73,8 +73,8 @@ use all defined FWU images. Other platforms may use a subset of these.  -3. Image Identification ------------------------ +3. Image Identification +------------------------ Each FWU image and certificate is identified by a unique ID, defined by the platform, which BL1 uses to fetch an image descriptor (`image_desc_t`) via a @@ -135,7 +135,7 @@ The following is a brief description of the supported states: 5. BL1 SMC Interface ------------------ +--------------------- ### BL1_SMC_CALL_COUNT diff --git a/docs/interrupt-framework-design.md b/docs/interrupt-framework-design.md index 060bbf2e..e50d1758 100644 --- a/docs/interrupt-framework-design.md +++ b/docs/interrupt-framework-design.md @@ -10,7 +10,7 @@ Contents : - [Valid Routing Models](#113-valid-routing-models) + [Secure-EL1 Interrupts](#1131-secure-el1-interrupts) + [Non-secure Interrupts](#1132-non-secure-interrupts) - + [EL3 interrupts](#1133-el3_interrupts) + + [EL3 interrupts](#1133-el3-interrupts) - [Mapping of Interrupt Type to Signal](#114-mapping-of-interrupt-type-to-signal) + [Effect of mapping of several interrupt types to one signal](#1141-effect-of-mapping-of-several-interrupt-types-to-one-signal) - [Assumptions in Interrupt Management Framework](#12-assumptions-in-interrupt-management-framework) diff --git a/include/lib/cpus/aarch64/cortex_a35.h b/include/lib/cpus/aarch64/cortex_a35.h new file mode 100644 index 00000000..4288b9f7 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a35.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CORTEX_A35_H__ +#define __CORTEX_A35_H__ + +/* Cortex-A35 Main ID register for revision 0 */ +#define CORTEX_A35_MIDR 0x410FD040 + +/******************************************************************************* + * CPU Extended Control register specific definitions. + * CPUECTLR_EL1 is an implementation-specific register. + ******************************************************************************/ +#define CORTEX_A35_CPUECTLR_EL1 S3_1_C15_C2_1 +#define CORTEX_A35_CPUECTLR_SMPEN_BIT (1 << 6) + +#endif /* __CORTEX_A35_H__ */ diff --git a/lib/cpus/aarch64/cortex_a35.S b/lib/cpus/aarch64/cortex_a35.S new file mode 100644 index 00000000..6a447c01 --- /dev/null +++ b/lib/cpus/aarch64/cortex_a35.S @@ -0,0 +1,164 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch.h> +#include <asm_macros.S> +#include <bl_common.h> +#include <cortex_a35.h> +#include <cpu_macros.S> +#include <plat_macros.S> + + /* --------------------------------------------- + * Disable L1 data cache and unified L2 cache + * --------------------------------------------- + */ +func cortex_a35_disable_dcache + mrs x1, sctlr_el3 + bic x1, x1, #SCTLR_C_BIT + msr sctlr_el3, x1 + isb + ret +endfunc cortex_a35_disable_dcache + + /* --------------------------------------------- + * Disable intra-cluster coherency + * --------------------------------------------- + */ +func cortex_a35_disable_smp + mrs x0, CORTEX_A35_CPUECTLR_EL1 + bic x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT + msr CORTEX_A35_CPUECTLR_EL1, x0 + isb + dsb sy + ret +endfunc cortex_a35_disable_smp + + /* ------------------------------------------------- + * The CPU Ops reset function for Cortex-A35. + * Clobbers: x0 + * ------------------------------------------------- + */ +func cortex_a35_reset_func + /* --------------------------------------------- + * As a bare minimum enable the SMP bit if it is + * not already set. + * --------------------------------------------- + */ + mrs x0, CORTEX_A35_CPUECTLR_EL1 + tst x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT + b.ne skip_smp_setup + orr x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT + msr CORTEX_A35_CPUECTLR_EL1, x0 +skip_smp_setup: + isb + ret +endfunc cortex_a35_reset_func + +func cortex_a35_core_pwr_dwn + mov x18, x30 + + /* --------------------------------------------- + * Turn off caches. + * --------------------------------------------- + */ + bl cortex_a35_disable_dcache + + /* --------------------------------------------- + * Flush L1 caches. + * --------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level1 + + /* --------------------------------------------- + * Come out of intra cluster coherency + * --------------------------------------------- + */ + mov x30, x18 + b cortex_a35_disable_smp +endfunc cortex_a35_core_pwr_dwn + +func cortex_a35_cluster_pwr_dwn + mov x18, x30 + + /* --------------------------------------------- + * Turn off caches. + * --------------------------------------------- + */ + bl cortex_a35_disable_dcache + + /* --------------------------------------------- + * Flush L1 caches. + * --------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level1 + + /* --------------------------------------------- + * Disable the optional ACP. + * --------------------------------------------- + */ + bl plat_disable_acp + + /* --------------------------------------------- + * Flush L2 caches. + * --------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level2 + + /* --------------------------------------------- + * Come out of intra cluster coherency + * --------------------------------------------- + */ + mov x30, x18 + b cortex_a35_disable_smp +endfunc cortex_a35_cluster_pwr_dwn + + /* --------------------------------------------- + * This function provides cortex_a35 specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_a35_regs, "aS" +cortex_a35_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_a35_cpu_reg_dump + adr x6, cortex_a35_regs + mrs x8, CORTEX_A35_CPUECTLR_EL1 + ret +endfunc cortex_a35_cpu_reg_dump + +declare_cpu_ops cortex_a35, CORTEX_A35_MIDR diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index cb5f5d7e..22df6d7e 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: @@ -64,6 +64,7 @@ PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/aarch64/fvp_common.c BL1_SOURCES += drivers/io/io_semihosting.c \ lib/cpus/aarch64/aem_generic.S \ + lib/cpus/aarch64/cortex_a35.S \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ lib/semihosting/semihosting.c \ @@ -87,6 +88,7 @@ BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ plat/arm/board/fvp/fvp_security.c BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \ + lib/cpus/aarch64/cortex_a35.S \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ plat/arm/board/fvp/fvp_bl31_setup.c \ |