diff options
27 files changed, 557 insertions, 214 deletions
@@ -138,9 +138,10 @@ msg_start: include plat/${PLAT}/platform.mk -# By default all CPU errata workarounds are disabled. This can be +# Include the CPU specific operations makefile. By default all CPU errata +# workarounds and CPU specifc optimisations are disabled. This can be # overridden by the platform. -include lib/cpus/cpu-errata.mk +include lib/cpus/cpu-ops.mk ifdef BL1_SOURCES NEED_BL1 := yes diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c index 51c55e01..a73946ed 100644 --- a/bl2/bl2_main.c +++ b/bl2/bl2_main.c @@ -199,9 +199,6 @@ void bl2_main(void) /* Perform remaining generic architectural setup in S-EL1 */ bl2_arch_setup(); - /* Perform platform setup in BL2 */ - bl2_platform_setup(); - /* * Load the subsequent bootloader images */ @@ -211,6 +208,9 @@ void bl2_main(void) panic(); } + /* Perform platform setup in BL2 after loading BL3-0 */ + bl2_platform_setup(); + /* * Get a pointer to the memory the platform has set aside to pass * information to BL3-1. diff --git a/docs/cpu-errata-workarounds.md b/docs/cpu-specific-build-macros.md index 8285d89d..246381a8 100644 --- a/docs/cpu-errata-workarounds.md +++ b/docs/cpu-specific-build-macros.md @@ -1,11 +1,28 @@ -ARM CPU Errata Workarounds -========================== +ARM CPU Specific Build Macros +============================= + +Contents +-------- + +1. Introduction +2. CPU Errata Workarounds +3. CPU Specific optimizations + +1. Introduction +---------------- + +This document describes the various build options present in the CPU specific +operations framework to enable errata workarounds and to enable optimizations +for a specific CPU on a platform. + +2. CPU Errata Workarounds +-------------------------- ARM Trusted Firmware exports a series of build flags which control the errata workarounds that are applied to each CPU by the reset handler. The errata details can be found in the CPU specifc errata documents published by ARM. The errata workarounds are implemented for a particular revision -or a set of processor revisions. This check is done in the debug build. +or a set of processor revisions. This is checked by reset handler at runtime. Each errata workaround is identified by its `ID` as specified in the processor's errata notice document. The format of the define used to enable/disable the errata is `ERRATA_<Processor name>_<ID>` where the `Processor name` @@ -13,7 +30,10 @@ is either `A57` for the `Cortex_A57` CPU or `A53` for `Cortex_A53` CPU. All workarounds are disabled by default. The platform is reponsible for enabling these workarounds according to its requirement by defining the -errata workaround build flags in the platform specific makefile. +errata workaround build flags in the platform specific makefile. In case +these workarounds are enabled for the wrong CPU revision then the errata +workaround is not applied. In the DEBUG build, this is indicated by +printing a warning to the crash console. In the current implementation, a platform which has more than 1 variant with different revisions of a processor has no runtime mechanism available @@ -22,14 +42,28 @@ for it to specify which errata workarounds should be enabled or not. The value of the build flags are 0 by default, that is, disabled. Any other value will enable it. -For Cortex A57, following errata build flags are defined : +For Cortex-A57, following errata build flags are defined : -* `ERRATA_A57_806969`: This applies errata 806969 workaround to cortex a57 +* `ERRATA_A57_806969`: This applies errata 806969 workaround to Cortex-A57 CPU. This needs to be enabled only for revision r0p0 of the CPU. -* `ERRATA_A57_813420`: This applies errata 813420 workaround to cortex a57 +* `ERRATA_A57_813420`: This applies errata 813420 workaround to Cortex-A57 CPU. This needs to be enabled only for revision r0p0 of the CPU. +3. CPU Specific optimizations +------------------------------ + +This section describes some of the optimizations allowed by the CPU micro +architecture that can be enabled by the platform as desired. + +* `SKIP_A57_L1_FLUSH_PWR_DWN`: This flag enables an optimization in the + Cortex-A57 cluster power down sequence by not flushing the Level 1 data + cache. The L1 data cache and the L2 unified cache are inclusive. A flush + of the L2 by set/way flushes any dirty lines from the L1 as well. This + is a known safe deviation from the Cortex-A57 TRM defined power down + sequence. Each Cortex-A57 based platform must make its own decision on + whether to use the optimization. + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _Copyright (c) 2014, ARM Limited and Contributors. All rights reserved._ diff --git a/docs/firmware-design.md b/docs/firmware-design.md index e952617b..bc075da3 100644 --- a/docs/firmware-design.md +++ b/docs/firmware-design.md @@ -982,9 +982,10 @@ Please note that only 2. is mandated by the TRM. The CPU specific operations framework scales to accommodate a large number of different CPUs during power down and reset handling. The platform can specify +any CPU optimization it wants to enable for each CPU. It can also specify the CPU errata workarounds to be applied for each CPU type during reset handling by defining CPU errata compile time macros. Details on these macros -can be found in the [cpu-errata-workarounds.md][ERRW] file. +can be found in the [cpu-specific-build-macros.md][CPUBM] file. The CPU specific operations framework depends on the `cpu_ops` structure which needs to be exported for each type of CPU in the platform. It is defined in @@ -1199,16 +1200,12 @@ sections must not overstep. The platform code must provide those. The following list describes the memory layout on the FVP: * A 4KB page of shared memory is used to store the entrypoint mailboxes - and the parameters passed between bootloaders. The shared memory can be - allocated either at the top of Trusted SRAM or at the base of Trusted - DRAM at build time. When allocated in Trusted SRAM, the amount of Trusted - SRAM available to load the bootloader images will be reduced by the size - of the shared memory. + and the parameters passed between bootloaders. The shared memory is located + at the base of the Trusted SRAM. The amount of Trusted SRAM available to + load the bootloader images will be reduced by the size of the shared memory. * BL1 is originally sitting in the Trusted ROM at address `0x0`. Its read-write data are relocated at the top of the Trusted SRAM at runtime. - If the shared memory is allocated in Trusted SRAM, the BL1 read-write data - is relocated just below the shared memory. * BL3-1 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will overwrite BL1 R/W data. @@ -1217,21 +1214,17 @@ The following list describes the memory layout on the FVP: * The TSP is loaded as the BL3-2 image at the base of either the Trusted SRAM or Trusted DRAM. When loaded into Trusted SRAM, its NOBITS sections - are allowed to overlay BL2. When loaded into Trusted DRAM, an offset - corresponding to the size of the shared memory is applied to avoid - overlap. + are allowed to overlay BL2. This memory layout is designed to give the BL3-2 image as much memory as possible when it is loaded into Trusted SRAM. Depending on the location of the -shared memory page and the TSP, it will result in different memory maps, -illustrated by the following diagrams. +TSP, it will result in different memory maps, illustrated by the following +diagrams. -**Shared data & TSP in Trusted SRAM (default option):** +**TSP in Trusted SRAM (default option):** Trusted SRAM - 0x04040000 +----------+ - | Shared | - 0x0403F000 +----------+ loaded by BL2 ------------------ + 0x04040000 +----------+ loaded by BL2 ------------------ | BL1 (rw) | <<<<<<<<<<<<< | BL3-1 NOBITS | |----------| <<<<<<<<<<<<< |----------------| | | <<<<<<<<<<<<< | BL3-1 PROGBITS | @@ -1239,7 +1232,9 @@ illustrated by the following diagrams. | BL2 | <<<<<<<<<<<<< | BL3-2 NOBITS | |----------| <<<<<<<<<<<<< |----------------| | | <<<<<<<<<<<<< | BL3-2 PROGBITS | - 0x04000000 +----------+ ------------------ + 0x04001000 +----------+ ------------------ + | Shared | + 0x04000000 +----------+ Trusted ROM 0x04000000 +----------+ @@ -1247,15 +1242,11 @@ illustrated by the following diagrams. 0x00000000 +----------+ -**Shared data & TSP in Trusted DRAM:** +**TSP in Trusted DRAM:** Trusted DRAM 0x08000000 +----------+ - | | | BL3-2 | - | | - 0x06001000 |----------| - | Shared | 0x06000000 +----------+ Trusted SRAM @@ -1267,6 +1258,8 @@ illustrated by the following diagrams. | BL2 | |----------| | | + 0x04001000 +----------+ + | Shared | 0x04000000 +----------+ Trusted ROM @@ -1274,37 +1267,46 @@ illustrated by the following diagrams. | BL1 (ro) | 0x00000000 +----------+ -**Shared data in Trusted DRAM, TSP in Trusted SRAM:** +Loading the TSP image in Trusted DRAM doesn't change the memory layout of the +other boot loader images in Trusted SRAM. - Trusted DRAM +#### Memory layout on Juno ARM development platform + +**TSP in Trusted SRAM (default option):** + + Flash0 + 0x0C000000 +----------+ + : : + 0x0BED0000 |----------| + | BL1 (ro) | + 0x0BEC0000 |----------| + : : + | Bypass | 0x08000000 +----------+ - | | - | | - | | - 0x06001000 |----------| - | Shared | - 0x06000000 +----------+ Trusted SRAM - 0x04040000 +----------+ loaded by BL2 ------------------ - | BL1 (rw) | <<<<<<<<<<<<< | BL3-1 NOBITS | - |----------| <<<<<<<<<<<<< |----------------| - | | <<<<<<<<<<<<< | BL3-1 PROGBITS | - |----------| ------------------ - | BL2 | <<<<<<<<<<<<< | BL3-2 NOBITS | - |----------| <<<<<<<<<<<<< |----------------| - | | <<<<<<<<<<<<< | BL3-2 PROGBITS | - 0x04000000 +----------+ ------------------ - - Trusted ROM + 0x04040000 +----------+ + | BL2 | BL3-1 is loaded + 0x04033000 |----------| after BL3-0 has + | BL3-2 | been sent to SCP + 0x04023000 |----------| ------------------ + | BL3-0 | <<<<<<<<<<<<< | BL3-1 | + 0x04009000 |----------| ------------------ + | BL1 (rw) | + 0x04001000 |----------| + | MHU | 0x04000000 +----------+ - | BL1 (ro) | - 0x00000000 +----------+ -Loading the TSP image in Trusted DRAM doesn't change the memory layout of the -other boot loader images in Trusted SRAM. +**TSP in the secure region of DRAM:** -#### Memory layout on Juno ARM development platform + DRAM + 0xFFE00000 +----------+ + | BL3-2 | + 0xFF000000 |----------| + | | + : : + | | + 0x80000000 +----------+ Flash0 0x0C000000 +----------+ @@ -1320,7 +1322,7 @@ other boot loader images in Trusted SRAM. 0x04040000 +----------+ | BL2 | BL3-1 is loaded 0x04033000 |----------| after BL3-0 has - | BL3-2 | been sent to SCP + | | been sent to SCP 0x04023000 |----------| ------------------ | BL3-0 | <<<<<<<<<<<<< | BL3-1 | 0x04009000 |----------| ------------------ @@ -1484,4 +1486,4 @@ _Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved._ [User Guide]: ./user-guide.md [Porting Guide]: ./porting-guide.md [INTRG]: ./interrupt-framework-design.md -[ERRW]: ./cpu-errata-workarounds.md +[CPUBM]: ./cpu-specific-build-macros.md.md diff --git a/docs/user-guide.md b/docs/user-guide.md index d3a92f9b..0b95a1bf 100644 --- a/docs/user-guide.md +++ b/docs/user-guide.md @@ -244,18 +244,19 @@ performed. #### FVP specific build options -* `FVP_SHARED_DATA_LOCATION`: location of the shared memory page. Available - options: - - `tsram` (default) : top of Trusted SRAM - - `tdram` : base of Trusted DRAM - * `FVP_TSP_RAM_LOCATION`: location of the TSP binary. Options: - - `tsram` (default) : base of Trusted SRAM - - `tdram` : Trusted DRAM (above shared data) + - `tsram` (default) : Trusted SRAM + - `tdram` : Trusted DRAM For a better understanding of FVP options, the FVP memory map is explained in the [Firmware Design]. +#### Juno specific build options + +* `PLAT_TSP_LOCATION`: location of the TSP binary. Options: + - `tsram` : Trusted SRAM (default option) + - `dram` : Secure region in DRAM (set by the TrustZone controller) + ### Creating a Firmware Image Package FIPs are automatically created as part of the build instructions described in diff --git a/drivers/arm/tzc400/tzc400.c b/drivers/arm/tzc400/tzc400.c index 3ab1f318..df52c9cf 100644 --- a/drivers/arm/tzc400/tzc400.c +++ b/drivers/arm/tzc400/tzc400.c @@ -243,7 +243,7 @@ void tzc_configure_region(uint32_t filters, /* Assign the region to a filter and set secure attributes */ tzc_write_region_attributes(tzc.base, region, - (sec_attr << REGION_ATTRIBUTES_SEC_SHIFT) | filters); + (sec_attr << REG_ATTR_SEC_SHIFT) | filters); /* * Specify which non-secure devices have permission to access this diff --git a/include/drivers/arm/tzc400.h b/include/drivers/arm/tzc400.h index ff8b49ae..d62e67bc 100644 --- a/include/drivers/arm/tzc400.h +++ b/include/drivers/arm/tzc400.h @@ -126,9 +126,12 @@ #define FAIL_ID_ID_SHIFT 0 /* Used along with 'tzc_region_attributes_t' below */ -#define REGION_ATTRIBUTES_SEC_SHIFT 30 -#define REGION_ATTRIBUTES_F_EN_SHIFT 0 -#define REGION_ATTRIBUTES_F_EN_MASK 0xf +#define REG_ATTR_SEC_SHIFT 30 +#define REG_ATTR_F_EN_SHIFT 0 +#define REG_ATTR_F_EN_MASK 0xf +#define REG_ATTR_FILTER_BIT(x) ((1 << x) << REG_ATTR_F_EN_SHIFT) +#define REG_ATTR_FILTER_BIT_ALL (REG_ATTR_F_EN_MASK << \ + REG_ATTR_F_EN_SHIFT) #define REGION_ID_ACCESS_NSAID_WR_EN_SHIFT 16 #define REGION_ID_ACCESS_NSAID_RD_EN_SHIFT 0 diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index e5b2bf8c..476c9c5c 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -38,7 +38,9 @@ #define MIDR_IMPL_MASK 0xff #define MIDR_IMPL_SHIFT 0x18 #define MIDR_VAR_SHIFT 20 +#define MIDR_VAR_BITS 4 #define MIDR_REV_SHIFT 0 +#define MIDR_REV_BITS 4 #define MIDR_PN_MASK 0xfff #define MIDR_PN_SHIFT 0x4 diff --git a/lib/aarch64/cache_helpers.S b/lib/aarch64/cache_helpers.S index 1c805504..dc601021 100644 --- a/lib/aarch64/cache_helpers.S +++ b/lib/aarch64/cache_helpers.S @@ -35,6 +35,9 @@ .globl inv_dcache_range .globl dcsw_op_louis .globl dcsw_op_all + .globl dcsw_op_level1 + .globl dcsw_op_level2 + .globl dcsw_op_level3 /* ------------------------------------------ * Clean+Invalidate from base address till @@ -81,6 +84,7 @@ inv_loop: * x0: The operation type (0-2), as defined in arch.h * x3: The last cache level to operate on * x9: clidr_el1 + * x10: The cache level to begin operation from * and will carry out the operation on each data cache from level 0 * to the level in x3 in sequence * @@ -93,12 +97,12 @@ inv_loop: mrs x9, clidr_el1 ubfx x3, x9, \shift, \fw lsl x3, x3, \ls + mov x10, xzr b do_dcsw_op .endm func do_dcsw_op cbz x3, exit - mov x10, xzr adr x14, dcsw_loop_table // compute inner loop address add x14, x14, x0, lsl #5 // inner loop is 8x32-bit instructions mov x0, x9 @@ -163,3 +167,45 @@ func dcsw_op_louis func dcsw_op_all dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT + + /* --------------------------------------------------------------- + * Helper macro for data cache operations by set/way for the + * level specified + * --------------------------------------------------------------- + */ + .macro dcsw_op_level level + mrs x9, clidr_el1 + mov x3, \level + sub x10, x3, #2 + b do_dcsw_op + .endm + + /* --------------------------------------------------------------- + * Data cache operations by set/way for level 1 cache + * + * The main function, do_dcsw_op requires: + * x0: The operation type (0-2), as defined in arch.h + * --------------------------------------------------------------- + */ +func dcsw_op_level1 + dcsw_op_level #(1 << LEVEL_SHIFT) + + /* --------------------------------------------------------------- + * Data cache operations by set/way for level 2 cache + * + * The main function, do_dcsw_op requires: + * x0: The operation type (0-2), as defined in arch.h + * --------------------------------------------------------------- + */ +func dcsw_op_level2 + dcsw_op_level #(2 << LEVEL_SHIFT) + + /* --------------------------------------------------------------- + * Data cache operations by set/way for level 3 cache + * + * The main function, do_dcsw_op requires: + * x0: The operation type (0-2), as defined in arch.h + * --------------------------------------------------------------- + */ +func dcsw_op_level3 + dcsw_op_level #(3 << LEVEL_SHIFT) diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S index 722ce7af..ec184641 100644 --- a/lib/cpus/aarch64/cortex_a53.S +++ b/lib/cpus/aarch64/cortex_a53.S @@ -77,11 +77,11 @@ func cortex_a53_core_pwr_dwn bl cortex_a53_disable_dcache /* --------------------------------------------- - * Flush L1 cache to PoU. + * Flush L1 caches. * --------------------------------------------- */ mov x0, #DCCISW - bl dcsw_op_louis + bl dcsw_op_level1 /* --------------------------------------------- * Come out of intra cluster coherency @@ -100,17 +100,24 @@ func cortex_a53_cluster_pwr_dwn bl cortex_a53_disable_dcache /* --------------------------------------------- + * Flush L1 caches. + * --------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level1 + + /* --------------------------------------------- * Disable the optional ACP. * --------------------------------------------- */ bl plat_disable_acp /* --------------------------------------------- - * Flush L1 and L2 caches to PoC. + * Flush L2 caches. * --------------------------------------------- */ mov x0, #DCCISW - bl dcsw_op_all + bl dcsw_op_level2 /* --------------------------------------------- * Come out of intra cluster coherency diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index eed1bbb9..dab16d7e 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -57,7 +57,7 @@ func cortex_a57_disable_l2_prefetch bic x0, x0, x1 msr CPUECTLR_EL1, x0 isb - dsb sy + dsb ish ret /* --------------------------------------------- @@ -81,33 +81,79 @@ func cortex_a57_disable_ext_debug dsb sy ret -func cortex_a57_reset_func -#if ERRATA_A57_806969 || ERRATA_A57_813420 - /* --------------------------------------------- - * Ensure that the following errata is only - * applied on r0p0 parts. - * --------------------------------------------- + /* -------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #806969. + * This applies only to revision r0p0 of Cortex A57. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * -------------------------------------------------- */ -#if ASM_ASSERTION - mrs x0, midr_el1 - ubfx x1, x0, #MIDR_VAR_SHIFT, #4 - ubfx x2, x0, #MIDR_REV_SHIFT, #4 - orr x0, x1, x2 - cmp x0, #0 - ASM_ASSERT(eq) +func errata_a57_806969_wa + /* + * Compare x0 against revision r0p0 + */ + cbz x0, apply_806969 +#if DEBUG + b print_revision_warning +#else + ret #endif - mov x1, xzr -#if ERRATA_A57_806969 +apply_806969: + mrs x1, CPUACTLR_EL1 orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA + msr CPUACTLR_EL1, x1 + ret + + + /* --------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #813420. + * This applies only to revision r0p0 of Cortex A57. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * --------------------------------------------------- + */ +func errata_a57_813420_wa + /* + * Compare x0 against revision r0p0 + */ + cbz x0, apply_813420 +#if DEBUG + b print_revision_warning +#else + ret #endif -#if ERRATA_A57_813420 +apply_813420: + mrs x1, CPUACTLR_EL1 orr x1, x1, #CPUACTLR_DCC_AS_DCCI -#endif - mrs x0, CPUACTLR_EL1 - orr x0, x0, x1 - msr CPUACTLR_EL1, x0 + msr CPUACTLR_EL1, x1 + ret + + /* ------------------------------------------------- + * The CPU Ops reset function for Cortex-A57. + * ------------------------------------------------- + */ +func cortex_a57_reset_func + mov x19, x30 + mrs x0, midr_el1 + + /* + * Extract the variant[20:23] and revision[0:3] from x0 + * and pack it in x20[0:7] as variant[4:7] and revision[0:3]. + * First extract x0[16:23] to x20[0:7] and zero fill the rest. + * Then extract x0[0:3] into x20[0:3] retaining other bits. + */ + ubfx x20, x0, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), #(MIDR_REV_BITS + MIDR_VAR_BITS) + bfxil x20, x0, #MIDR_REV_SHIFT, #MIDR_REV_BITS + +#if ERRATA_A57_806969 + mov x0, x20 + bl errata_a57_806969_wa #endif +#if ERRATA_A57_813420 + mov x0, x20 + bl errata_a57_813420_wa +#endif /* --------------------------------------------- * As a bare minimum enable the SMP bit. * --------------------------------------------- @@ -116,8 +162,12 @@ func cortex_a57_reset_func orr x0, x0, #CPUECTLR_SMP_BIT msr CPUECTLR_EL1, x0 isb - ret + ret x19 + /* ---------------------------------------------------- + * The CPU Ops core power down function for Cortex-A57. + * ---------------------------------------------------- + */ func cortex_a57_core_pwr_dwn mov x18, x30 @@ -134,11 +184,11 @@ func cortex_a57_core_pwr_dwn bl cortex_a57_disable_l2_prefetch /* --------------------------------------------- - * Flush L1 cache to PoU. + * Flush L1 caches. * --------------------------------------------- */ mov x0, #DCCISW - bl dcsw_op_louis + bl dcsw_op_level1 /* --------------------------------------------- * Come out of intra cluster coherency @@ -153,6 +203,10 @@ func cortex_a57_core_pwr_dwn mov x30, x18 b cortex_a57_disable_ext_debug + /* ------------------------------------------------------- + * The CPU Ops cluster power down function for Cortex-A57. + * ------------------------------------------------------- + */ func cortex_a57_cluster_pwr_dwn mov x18, x30 @@ -168,18 +222,26 @@ func cortex_a57_cluster_pwr_dwn */ bl cortex_a57_disable_l2_prefetch +#if !SKIP_A57_L1_FLUSH_PWR_DWN + /* ------------------------------------------------- + * Flush the L1 caches. + * ------------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level1 +#endif /* --------------------------------------------- * Disable the optional ACP. * --------------------------------------------- */ bl plat_disable_acp - /* --------------------------------------------- - * Flush L1 and L2 caches to PoC. - * --------------------------------------------- + /* ------------------------------------------------- + * Flush the L2 caches. + * ------------------------------------------------- */ mov x0, #DCCISW - bl dcsw_op_all + bl dcsw_op_level2 /* --------------------------------------------- * Come out of intra cluster coherency diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S index 46584b3f..f053d44f 100644 --- a/lib/cpus/aarch64/cpu_helpers.S +++ b/lib/cpus/aarch64/cpu_helpers.S @@ -45,7 +45,7 @@ */ .globl reset_handler func reset_handler - mov x10, x30 + mov x19, x30 bl plat_reset_handler @@ -58,10 +58,11 @@ func reset_handler /* Get the cpu_ops reset handler */ ldr x2, [x0, #CPU_RESET_FUNC] + mov x30, x19 cbz x2, 1f - blr x2 + br x2 1: - ret x10 + ret #endif /* IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31) */ @@ -191,3 +192,29 @@ func get_cpu_ops_ptr sub x0, x4, #(CPU_OPS_SIZE + CPU_MIDR) error_exit: ret + +#if DEBUG + /* + * This function prints a warning message to the crash console + * if the CPU revision/part number does not match the errata + * workaround enabled in the build. + * Clobber: x30, x0 - x5 + */ +.section .rodata.rev_warn_str, "aS" +rev_warn_str: + .asciz "Warning: Skipping Errata workaround for non matching CPU revision number.\n" + + .globl print_revision_warning +func print_revision_warning + mov x5, x30 + /* Ensure the console is initialized */ + bl plat_crash_console_init + /* Check if the console is initialized */ + cbz x0, 1f + /* The console is initialized */ + adr x4, rev_warn_str + bl asm_print_str +1: + ret x5 +#endif + diff --git a/lib/cpus/cpu-errata.mk b/lib/cpus/cpu-ops.mk index 79f0156d..1c5512e9 100644 --- a/lib/cpus/cpu-errata.mk +++ b/lib/cpus/cpu-ops.mk @@ -28,6 +28,15 @@ # POSSIBILITY OF SUCH DAMAGE. # +# Cortex A57 specific optimisation to skip L1 cache flush when +# cluster is powered down. +SKIP_A57_L1_FLUSH_PWR_DWN ?=0 + +# Process SKIP_A57_L1_FLUSH_PWR_DWN flag +$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN)) +$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN)) + + # CPU Errata Build flags. These should be enabled by the # platform if the errata needs to be applied. diff --git a/plat/fvp/aarch64/fvp_common.c b/plat/fvp/aarch64/fvp_common.c index e393ceda..987f48f6 100644 --- a/plat/fvp/aarch64/fvp_common.c +++ b/plat/fvp/aarch64/fvp_common.c @@ -50,8 +50,8 @@ ******************************************************************************/ plat_config_t plat_config; -#define MAP_SHARED_RAM MAP_REGION_FLAT(FVP_SHARED_RAM_BASE, \ - FVP_SHARED_RAM_SIZE, \ +#define MAP_SHARED_RAM MAP_REGION_FLAT(FVP_SHARED_MEM_BASE, \ + FVP_SHARED_MEM_SIZE, \ MT_MEMORY | MT_RW | MT_SECURE) #define MAP_FLASH0 MAP_REGION_FLAT(FLASH0_BASE, \ diff --git a/plat/fvp/bl2_fvp_setup.c b/plat/fvp/bl2_fvp_setup.c index 2c26d971..67f89bc4 100644 --- a/plat/fvp/bl2_fvp_setup.c +++ b/plat/fvp/bl2_fvp_setup.c @@ -74,7 +74,7 @@ __attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE), /* Assert that BL3-1 parameters fit in shared memory */ CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t)) < - (FVP_SHARED_RAM_BASE + FVP_SHARED_RAM_SIZE), + (FVP_SHARED_MEM_BASE + FVP_SHARED_MEM_SIZE), assert_bl31_params_do_not_fit_in_shared_memory); /******************************************************************************* diff --git a/plat/fvp/fvp_def.h b/plat/fvp/fvp_def.h index 9914f69a..99c23d8d 100644 --- a/plat/fvp/fvp_def.h +++ b/plat/fvp/fvp_def.h @@ -35,7 +35,7 @@ #define FIP_IMAGE_NAME "fip.bin" #define FVP_PRIMARY_CPU 0x0 -/* Memory location options for Shared data and TSP in FVP */ +/* Memory location options for TSP */ #define FVP_IN_TRUSTED_SRAM 0 #define FVP_IN_TRUSTED_DRAM 1 @@ -46,8 +46,13 @@ #define FVP_TRUSTED_ROM_BASE 0x00000000 #define FVP_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ -#define FVP_TRUSTED_SRAM_BASE 0x04000000 -#define FVP_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ +/* The first 4KB of Trusted SRAM are used as shared memory */ +#define FVP_SHARED_MEM_BASE 0x04000000 +#define FVP_SHARED_MEM_SIZE 0x00001000 /* 4 KB */ + +/* The remaining Trusted SRAM is used to load the BL images */ +#define FVP_TRUSTED_SRAM_BASE 0x04001000 +#define FVP_TRUSTED_SRAM_SIZE 0x0003F000 /* 252 KB */ #define FVP_TRUSTED_DRAM_BASE 0x06000000 #define FVP_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */ @@ -74,28 +79,6 @@ #define NSRAM_BASE 0x2e000000 #define NSRAM_SIZE 0x10000 -/* 4KB shared memory */ -#define FVP_SHARED_RAM_SIZE 0x1000 - -/* Location of shared memory */ -#if (FVP_SHARED_DATA_LOCATION_ID == FVP_IN_TRUSTED_DRAM) -/* Shared memory at the base of Trusted DRAM */ -# define FVP_SHARED_RAM_BASE FVP_TRUSTED_DRAM_BASE -# define FVP_TRUSTED_SRAM_LIMIT (FVP_TRUSTED_SRAM_BASE \ - + FVP_TRUSTED_SRAM_SIZE) -#elif (FVP_SHARED_DATA_LOCATION_ID == FVP_IN_TRUSTED_SRAM) -# if (FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_DRAM) -# error "Shared data in Trusted SRAM and TSP in Trusted DRAM is not supported" -# endif -/* Shared memory at the top of the Trusted SRAM */ -# define FVP_SHARED_RAM_BASE (FVP_TRUSTED_SRAM_BASE \ - + FVP_TRUSTED_SRAM_SIZE \ - - FVP_SHARED_RAM_SIZE) -# define FVP_TRUSTED_SRAM_LIMIT FVP_SHARED_RAM_BASE -#else -# error "Unsupported FVP_SHARED_DATA_LOCATION_ID value" -#endif - #define DRAM1_BASE 0x80000000ull #define DRAM1_SIZE 0x80000000ull #define DRAM1_END (DRAM1_BASE + DRAM1_SIZE - 1) @@ -268,7 +251,7 @@ ******************************************************************************/ /* Entrypoint mailboxes */ -#define MBOX_BASE FVP_SHARED_RAM_BASE +#define MBOX_BASE FVP_SHARED_MEM_BASE #define MBOX_SIZE 0x200 /* Base address where parameters to BL31 are stored */ diff --git a/plat/fvp/include/platform_def.h b/plat/fvp/include/platform_def.h index 32f070ff..5364a3da 100644 --- a/plat/fvp/include/platform_def.h +++ b/plat/fvp/include/platform_def.h @@ -93,12 +93,13 @@ #define BL1_RO_LIMIT (FVP_TRUSTED_ROM_BASE \ + FVP_TRUSTED_ROM_SIZE) /* - * Put BL1 RW at the top of the Trusted SRAM (just below the shared memory, if - * present). BL1_RW_BASE is calculated using the current BL1 RW debug size plus - * a little space for growth. + * Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using + * the current BL1 RW debug size plus a little space for growth. */ -#define BL1_RW_BASE (FVP_TRUSTED_SRAM_LIMIT - 0x6000) -#define BL1_RW_LIMIT FVP_TRUSTED_SRAM_LIMIT +#define BL1_RW_BASE (FVP_TRUSTED_SRAM_BASE \ + + FVP_TRUSTED_SRAM_SIZE - 0x6000) +#define BL1_RW_LIMIT (FVP_TRUSTED_SRAM_BASE \ + + FVP_TRUSTED_SRAM_SIZE) /******************************************************************************* * BL2 specific defines. @@ -114,13 +115,14 @@ * BL31 specific defines. ******************************************************************************/ /* - * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if - * present). BL31_BASE is calculated using the current BL3-1 debug size plus a - * little space for growth. + * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the + * current BL3-1 debug size plus a little space for growth. */ -#define BL31_BASE (FVP_TRUSTED_SRAM_LIMIT - 0x1D000) +#define BL31_BASE (FVP_TRUSTED_SRAM_BASE \ + + FVP_TRUSTED_SRAM_SIZE - 0x1D000) #define BL31_PROGBITS_LIMIT BL1_RW_BASE -#define BL31_LIMIT FVP_TRUSTED_SRAM_LIMIT +#define BL31_LIMIT (FVP_TRUSTED_SRAM_BASE \ + + FVP_TRUSTED_SRAM_SIZE) /******************************************************************************* * BL32 specific defines. @@ -137,8 +139,7 @@ #elif FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_DRAM # define TSP_SEC_MEM_BASE FVP_TRUSTED_DRAM_BASE # define TSP_SEC_MEM_SIZE FVP_TRUSTED_DRAM_SIZE -# define BL32_BASE (FVP_TRUSTED_DRAM_BASE \ - + FVP_SHARED_RAM_SIZE) +# define BL32_BASE FVP_TRUSTED_DRAM_BASE # define BL32_LIMIT (FVP_TRUSTED_DRAM_BASE + (1 << 21)) #else # error "Unsupported FVP_TSP_RAM_LOCATION_ID value" diff --git a/plat/fvp/platform.mk b/plat/fvp/platform.mk index e7c06a80..fdcee50b 100644 --- a/plat/fvp/platform.mk +++ b/plat/fvp/platform.mk @@ -28,17 +28,6 @@ # POSSIBILITY OF SUCH DAMAGE. # -# Shared memory may be allocated at the top of Trusted SRAM (tsram) or at the -# base of Trusted SRAM (tdram) -FVP_SHARED_DATA_LOCATION := tsram -ifeq (${FVP_SHARED_DATA_LOCATION}, tsram) - FVP_SHARED_DATA_LOCATION_ID := FVP_IN_TRUSTED_SRAM -else ifeq (${FVP_SHARED_DATA_LOCATION}, tdram) - FVP_SHARED_DATA_LOCATION_ID := FVP_IN_TRUSTED_DRAM -else - $(error "Unsupported FVP_SHARED_DATA_LOCATION value") -endif - # On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM. # Trusted SRAM is the default. FVP_TSP_RAM_LOCATION := tsram @@ -50,14 +39,7 @@ else $(error "Unsupported FVP_TSP_RAM_LOCATION value") endif -ifeq (${FVP_SHARED_DATA_LOCATION}, tsram) - ifeq (${FVP_TSP_RAM_LOCATION}, tdram) - $(error Shared data in Trusted SRAM and TSP in Trusted DRAM is not supported) - endif -endif - # Process flags -$(eval $(call add_define,FVP_SHARED_DATA_LOCATION_ID)) $(eval $(call add_define,FVP_TSP_RAM_LOCATION_ID)) PLAT_INCLUDES := -Iplat/fvp/include/ diff --git a/plat/juno/aarch64/juno_common.c b/plat/juno/aarch64/juno_common.c index 70b2f52f..8129b051 100644 --- a/plat/juno/aarch64/juno_common.c +++ b/plat/juno/aarch64/juno_common.c @@ -61,9 +61,14 @@ DEVICE1_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) -#define MAP_DRAM MAP_REGION_FLAT(DRAM_BASE, \ - DRAM_SIZE, \ +#define MAP_NS_DRAM MAP_REGION_FLAT(DRAM_NS_BASE, \ + DRAM_NS_SIZE, \ MT_MEMORY | MT_RW | MT_NS) + +#define MAP_TSP_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \ + TSP_SEC_MEM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + /* * Table of regions for different BL stages to map using the MMU. * This doesn't include Trusted RAM as the 'mem_layout' argument passed to @@ -86,7 +91,8 @@ static const mmap_region_t juno_mmap[] = { MAP_IOFPGA, MAP_DEVICE0, MAP_DEVICE1, - MAP_DRAM, + MAP_NS_DRAM, + MAP_TSP_MEM, {0} }; #endif diff --git a/plat/juno/bl1_plat_setup.c b/plat/juno/bl1_plat_setup.c index 5804682c..e27e3948 100644 --- a/plat/juno/bl1_plat_setup.c +++ b/plat/juno/bl1_plat_setup.c @@ -37,7 +37,6 @@ #include <mmio.h> #include <platform.h> #include <platform_def.h> -#include <tzc400.h> #include "../../bl1/bl1_private.h" #include "juno_def.h" #include "juno_private.h" @@ -150,36 +149,6 @@ static void init_nic400(void) } -static void init_tzc400(void) -{ - /* Enable all filter units available */ - mmio_write_32(TZC400_BASE + GATE_KEEPER_OFF, 0x0000000f); - - /* - * Secure read and write are enabled for region 0, and the background - * region (region 0) is enabled for all four filter units - */ - mmio_write_32(TZC400_BASE + REGION_ATTRIBUTES_OFF, 0xc0000000); - - /* - * Enable Non-secure read/write accesses for the Soc Devices from the - * Non-Secure World - */ - mmio_write_32(TZC400_BASE + REGION_ID_ACCESS_OFF, - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_SCP) | - TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT) - ); -} - #define PCIE_SECURE_REG 0x3000 #define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1)) /* REG and MEM access bits */ @@ -200,7 +169,6 @@ static void init_pcie(void) void bl1_platform_setup(void) { init_nic400(); - init_tzc400(); init_pcie(); /* Initialise the IO layer and register platform IO devices */ diff --git a/plat/juno/bl2_plat_setup.c b/plat/juno/bl2_plat_setup.c index 717cfbb2..900a587f 100644 --- a/plat/juno/bl2_plat_setup.c +++ b/plat/juno/bl2_plat_setup.c @@ -162,6 +162,9 @@ void bl2_early_platform_setup(meminfo_t *mem_layout) /* Setup the BL2 memory layout */ bl2_tzram_layout = *mem_layout; + + /* Initialise the IO layer and register platform IO devices */ + io_setup(); } /******************************************************************************* @@ -171,8 +174,8 @@ void bl2_early_platform_setup(meminfo_t *mem_layout) ******************************************************************************/ void bl2_platform_setup(void) { - /* Initialise the IO layer and register platform IO devices */ - io_setup(); + /* Initialize the secure environment */ + plat_security_setup(); } /* Flush the TF params and the TF plat params */ @@ -309,8 +312,8 @@ void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) ******************************************************************************/ void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) { - bl33_meminfo->total_base = DRAM_BASE; - bl33_meminfo->total_size = DRAM_SIZE; - bl33_meminfo->free_base = DRAM_BASE; - bl33_meminfo->free_size = DRAM_SIZE; + bl33_meminfo->total_base = DRAM_NS_BASE; + bl33_meminfo->total_size = DRAM_NS_SIZE; + bl33_meminfo->free_base = DRAM_NS_BASE; + bl33_meminfo->free_size = DRAM_NS_SIZE; } diff --git a/plat/juno/include/platform_def.h b/plat/juno/include/platform_def.h index 6d9d0fb0..e746d028 100644 --- a/plat/juno/include/platform_def.h +++ b/plat/juno/include/platform_def.h @@ -125,10 +125,20 @@ /******************************************************************************* * BL3-2 specific defines. ******************************************************************************/ -#define TSP_SEC_MEM_BASE TZRAM_BASE -#define TSP_SEC_MEM_SIZE TZRAM_SIZE -#define BL32_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1d000) -#define BL32_LIMIT BL2_BASE +#if (PLAT_TSP_LOCATION_ID == PLAT_TRUSTED_SRAM_ID) +# define TSP_SEC_MEM_BASE TZRAM_BASE +# define TSP_SEC_MEM_SIZE TZRAM_SIZE +# define BL32_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1d000) +# define BL32_LIMIT BL2_BASE +#elif (PLAT_TSP_LOCATION_ID == PLAT_DRAM_ID) +# define TSP_SEC_MEM_BASE DRAM_SEC_BASE +# define TSP_SEC_MEM_SIZE (DRAM_SEC_SIZE - DRAM_SCP_SIZE) +# define BL32_BASE DRAM_SEC_BASE +# define BL32_LIMIT (DRAM_SEC_BASE + DRAM_SEC_SIZE - \ + DRAM_SCP_SIZE) +#else +# error "Unsupported PLAT_TSP_LOCATION_ID value" +#endif /******************************************************************************* * Load address of BL3-3 in the Juno port @@ -139,7 +149,15 @@ * Platform specific page table and MMU setup constants ******************************************************************************/ #define ADDR_SPACE_SIZE (1ull << 32) -#define MAX_XLAT_TABLES 2 + +#if IMAGE_BL1 || IMAGE_BL31 +# define MAX_XLAT_TABLES 2 +#endif + +#if IMAGE_BL2 || IMAGE_BL32 +# define MAX_XLAT_TABLES 3 +#endif + #define MAX_MMAP_REGIONS 16 /******************************************************************************* diff --git a/plat/juno/juno_def.h b/plat/juno/juno_def.h index 15296ed8..88e35b0d 100644 --- a/plat/juno/juno_def.h +++ b/plat/juno/juno_def.h @@ -37,6 +37,9 @@ /******************************************************************************* * Juno memory map related constants ******************************************************************************/ +#define PLAT_TRUSTED_SRAM_ID 0 +#define PLAT_DRAM_ID 1 + #define MHU_SECURE_BASE 0x04000000 #define MHU_SECURE_SIZE 0x00001000 @@ -73,6 +76,26 @@ #define DRAM_BASE 0x80000000 #define DRAM_SIZE 0x80000000 +/* + * DRAM at 0x8000_0000 is divided in two regions: + * - Secure DRAM (default is the top 16MB except for the last 2MB, which are + * used by the SCP for DDR retraining) + * - Non-Secure DRAM (remaining DRAM starting at DRAM_BASE) + */ + +#define DRAM_SCP_SIZE 0x00200000 +#define DRAM_SCP_BASE (DRAM_BASE + DRAM_SIZE - DRAM_SCP_SIZE) + +#define DRAM_SEC_SIZE 0x00E00000 +#define DRAM_SEC_BASE (DRAM_SCP_BASE - DRAM_SEC_SIZE) + +#define DRAM_NS_BASE DRAM_BASE +#define DRAM_NS_SIZE (DRAM_SIZE - DRAM_SCP_SIZE - DRAM_SEC_SIZE) + +/* Second region of DRAM */ +#define DRAM2_BASE 0x880000000 +#define DRAM2_SIZE 0x180000000 + /* Memory mapped Generic timer interfaces */ #define SYS_CNTCTL_BASE 0x2a430000 #define SYS_CNTREAD_BASE 0x2a800000 diff --git a/plat/juno/juno_private.h b/plat/juno/juno_private.h index a6d1a1af..14d7af4d 100644 --- a/plat/juno/juno_private.h +++ b/plat/juno/juno_private.h @@ -97,6 +97,9 @@ int plat_get_image_source(const char *image_name, uintptr_t *dev_handle, uintptr_t *image_spec); +/* Declarations for security.c */ +void plat_security_setup(void); + /* * Before calling this function BL2 is loaded in memory and its entrypoint * is set by load_image. This is a placeholder for the platform to change diff --git a/plat/juno/plat_pm.c b/plat/juno/plat_pm.c index 8409b0c3..adf599f4 100644 --- a/plat/juno/plat_pm.c +++ b/plat/juno/plat_pm.c @@ -276,12 +276,47 @@ static void __dead2 juno_system_reset(void) } /******************************************************************************* + * Handler called when an affinity instance is about to enter standby. + ******************************************************************************/ +int32_t juno_affinst_standby(unsigned int power_state) +{ + unsigned int target_afflvl; + unsigned int scr; + + /* Sanity check the requested state */ + target_afflvl = psci_get_pstate_afflvl(power_state); + + /* + * It's possible to enter standby only on affinity level 0 i.e. a cpu + * on the Juno. Ignore any other affinity level. + */ + if (target_afflvl != MPIDR_AFFLVL0) + return PSCI_E_INVALID_PARAMS; + + scr = read_scr_el3(); + /* Enable PhysicalIRQ bit for NS world to wake the CPU */ + write_scr_el3(scr | SCR_IRQ_BIT); + isb(); + dsb(); + wfi(); + + /* + * Restore SCR to the original value, synchronisation of scr_el3 is + * done by eret while el3_exit to save some execution cycles. + */ + write_scr_el3(scr); + + return PSCI_E_SUCCESS; +} + +/******************************************************************************* * Export the platform handlers to enable psci to invoke them ******************************************************************************/ static const plat_pm_ops_t juno_ops = { .affinst_on = juno_affinst_on, .affinst_on_finish = juno_affinst_on_finish, .affinst_off = juno_affinst_off, + .affinst_standby = juno_affinst_standby, .affinst_suspend = juno_affinst_suspend, .affinst_suspend_finish = juno_affinst_suspend_finish, .system_off = juno_system_off, diff --git a/plat/juno/plat_security.c b/plat/juno/plat_security.c new file mode 100644 index 00000000..64e493f6 --- /dev/null +++ b/plat/juno/plat_security.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <debug.h> +#include <tzc400.h> +#include "juno_def.h" + +/******************************************************************************* + * Initialize the TrustZone Controller. Configure Region 0 with Secure RW access + * and allow Non-Secure masters full access + ******************************************************************************/ +static void init_tzc400(void) +{ + tzc_init(TZC400_BASE); + + /* Disable filters. */ + tzc_disable_filters(); + + /* Region 1 set to cover Non-Secure DRAM at 0x8000_0000. Apply the + * same configuration to all filters in the TZC. */ + tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 1, + DRAM_NS_BASE, DRAM_NS_BASE + DRAM_NS_SIZE - 1, + TZC_REGION_S_NONE, + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)); + + /* Region 2 set to cover Secure DRAM */ + tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 2, + DRAM_SEC_BASE, DRAM_SEC_BASE + DRAM_SEC_SIZE - 1, + TZC_REGION_S_RDWR, + 0); + + /* Region 3 set to cover DRAM used by SCP for DDR retraining */ + tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 3, + DRAM_SCP_BASE, DRAM_SCP_BASE + DRAM_SCP_SIZE - 1, + TZC_REGION_S_NONE, + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_SCP)); + + /* Region 4 set to cover Non-Secure DRAM at 0x8_8000_0000 */ + tzc_configure_region(REG_ATTR_FILTER_BIT_ALL, 4, + DRAM2_BASE, DRAM2_BASE + DRAM2_SIZE - 1, + TZC_REGION_S_NONE, + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)); + + /* Raise an exception if a NS device tries to access secure memory */ + tzc_set_action(TZC_ACTION_ERR); + + /* Enable filters. */ + tzc_enable_filters(); +} + +/******************************************************************************* + * Initialize the secure environment. At this moment only the TrustZone + * Controller is initialized. + ******************************************************************************/ +void plat_security_setup(void) +{ + /* Initialize the TrustZone Controller */ + init_tzc400(); +} diff --git a/plat/juno/platform.mk b/plat/juno/platform.mk index f0904ef0..6ca219d9 100644 --- a/plat/juno/platform.mk +++ b/plat/juno/platform.mk @@ -28,6 +28,23 @@ # POSSIBILITY OF SUCH DAMAGE. # +# On Juno, the Secure Payload can be loaded either in Trusted SRAM (default) or +# Secure DRAM allocated by the TrustZone Controller. + +PLAT_TSP_LOCATION := tsram + +ifeq (${PLAT_TSP_LOCATION}, tsram) + PLAT_TSP_LOCATION_ID := PLAT_TRUSTED_SRAM_ID +else ifeq (${PLAT_TSP_LOCATION}, dram) + PLAT_TSP_LOCATION_ID := PLAT_DRAM_ID +else + $(error "Unsupported PLAT_TSP_LOCATION value") +endif + +# Process flags +$(eval $(call add_define,PLAT_TSP_LOCATION_ID)) + + PLAT_INCLUDES := -Iplat/juno/include/ PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \ @@ -48,10 +65,12 @@ BL1_SOURCES += drivers/arm/cci400/cci400.c \ plat/juno/aarch64/plat_helpers.S \ plat/juno/aarch64/juno_common.c -BL2_SOURCES += lib/locks/bakery/bakery_lock.c \ +BL2_SOURCES += drivers/arm/tzc400/tzc400.c \ + lib/locks/bakery/bakery_lock.c \ plat/common/aarch64/platform_up_stack.S \ plat/juno/bl2_plat_setup.c \ plat/juno/mhu.c \ + plat/juno/plat_security.c \ plat/juno/aarch64/plat_helpers.S \ plat/juno/aarch64/juno_common.c \ plat/juno/scp_bootloader.c \ @@ -82,3 +101,7 @@ NEED_BL30 := yes # Enable workarounds for selected Cortex-A57 erratas. ERRATA_A57_806969 := 1 ERRATA_A57_813420 := 1 + +# Enable option to skip L1 data cache flush during the Cortex-A57 cluster +# power down sequence +SKIP_A57_L1_FLUSH_PWR_DWN := 1 |