diff options
Diffstat (limited to 'bl1')
| -rw-r--r-- | bl1/aarch64/bl1_arch_setup.c | 11 | ||||
| -rw-r--r-- | bl1/aarch64/bl1_entrypoint.S | 34 |
2 files changed, 16 insertions, 29 deletions
diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c index cf69ac7f..eeaa24af 100644 --- a/bl1/aarch64/bl1_arch_setup.c +++ b/bl1/aarch64/bl1_arch_setup.c @@ -37,20 +37,11 @@ ******************************************************************************/ void bl1_arch_setup(void) { - unsigned long tmp_reg = 0; - - /* Enable alignment checks */ - tmp_reg = read_sctlr_el3(); - tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT); - write_sctlr_el3(tmp_reg); - isb(); - /* * Set the next EL to be AArch64, route external abort and SError * interrupts to EL3 */ - tmp_reg = SCR_RES1_BITS | SCR_RW_BIT | SCR_EA_BIT; - write_scr(tmp_reg); + write_scr_el3(SCR_RES1_BITS | SCR_RW_BIT | SCR_EA_BIT); /* * Enable SError and Debug exceptions diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S index 50cfae65..dd7d78fe 100644 --- a/bl1/aarch64/bl1_entrypoint.S +++ b/bl1/aarch64/bl1_entrypoint.S @@ -44,7 +44,7 @@ func bl1_entrypoint /* --------------------------------------------- * Set the CPU endianness before doing anything - * that might involve memory reads or writes + * that might involve memory reads or writes. * --------------------------------------------- */ mrs x0, sctlr_el3 @@ -59,12 +59,14 @@ func bl1_entrypoint */ bl cpu_reset_handler - /* ------------------------------- - * Enable the instruction cache. - * ------------------------------- + /* --------------------------------------------- + * Enable the instruction cache, stack pointer + * and data access alignment checks + * --------------------------------------------- */ + mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) mrs x0, sctlr_el3 - orr x0, x0, #SCTLR_I_BIT + orr x0, x0, x1 msr sctlr_el3, x0 isb @@ -130,14 +132,16 @@ func bl1_entrypoint ldr x2, =__DATA_SIZE__ bl memcpy16 - /* --------------------------------------------- - * Give ourselves a small coherent stack to - * ease the pain of initializing the MMU and - * CCI in assembler - * --------------------------------------------- + /* -------------------------------------------- + * Allocate a stack whose memory will be marked + * as Normal-IS-WBWA when the MMU is enabled. + * There is no risk of reading stale stack + * memory after enabling the MMU as only the + * primary cpu is running at the moment. + * -------------------------------------------- */ mrs x0, mpidr_el1 - bl platform_set_coherent_stack + bl platform_set_stack /* --------------------------------------------- * Architectural init. can be generic e.g. @@ -150,14 +154,6 @@ func bl1_entrypoint bl bl1_early_platform_setup bl bl1_plat_arch_setup - /* --------------------------------------------- - * Give ourselves a stack allocated in Normal - * -IS-WBWA memory - * --------------------------------------------- - */ - mrs x0, mpidr_el1 - bl platform_set_stack - /* -------------------------------------------------- * Initialize platform and jump to our c-entry point * for this type of reset. Panic if it returns |