diff options
Diffstat (limited to 'bl31')
| -rw-r--r-- | bl31/aarch64/bl31_arch_setup.c | 14 | ||||
| -rw-r--r-- | bl31/aarch64/bl31_entrypoint.S | 8 | ||||
| -rw-r--r-- | bl31/aarch64/runtime_exceptions.S | 6 |
3 files changed, 16 insertions, 12 deletions
diff --git a/bl31/aarch64/bl31_arch_setup.c b/bl31/aarch64/bl31_arch_setup.c index f67881e6..a88b029e 100644 --- a/bl31/aarch64/bl31_arch_setup.c +++ b/bl31/aarch64/bl31_arch_setup.c @@ -42,18 +42,8 @@ ******************************************************************************/ void bl31_arch_setup(void) { - /* - * Route external abort and SError interrupts to EL3 - * other SCR bits will be configured before exiting to a lower exception - * level - */ - write_scr_el3(SCR_RES1_BITS | SCR_EA_BIT); - - /* - * Enable SError and Debug exceptions - */ - enable_serror(); - enable_debug_exceptions(); + /* Set the RES1 bits in the SCR_EL3 */ + write_scr_el3(SCR_RES1_BITS); /* Program the counter frequency */ write_cntfrq_el0(plat_get_syscnt_freq()); diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index c3a09bf3..a088c2e0 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -98,6 +98,14 @@ func bl31_entrypoint */ adr x1, runtime_exceptions msr vbar_el3, x1 + isb + + /* --------------------------------------------- + * Enable the SError interrupt now that the + * exception vectors have been setup. + * --------------------------------------------- + */ + msr daifclr, #DAIF_ABT_BIT /* --------------------------------------------------------------------- * The initial state of the Architectural feature trap register diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index 996dedcb..f5be9e07 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -44,6 +44,9 @@ * ----------------------------------------------------- */ .macro handle_sync_exception + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] mrs x30, esr_el3 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH @@ -70,6 +73,9 @@ * ----------------------------------------------------- */ .macro handle_interrupt_exception label + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] bl save_gp_registers |