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Diffstat (limited to 'docs/porting-guide.md')
| -rw-r--r-- | docs/porting-guide.md | 97 |
1 files changed, 45 insertions, 52 deletions
diff --git a/docs/porting-guide.md b/docs/porting-guide.md index 813d0be6..c7115903 100644 --- a/docs/porting-guide.md +++ b/docs/porting-guide.md @@ -15,6 +15,7 @@ Contents * Boot Loader stage 3-1 (BL3-1) * PSCI implementation (in BL3-1) * Interrupt Management framework (in BL3-1) + * Crash Reporting mechanism (in BL3-1) 4. C Library 5. Storage abstraction layer @@ -104,12 +105,6 @@ file is found in [plat/fvp/include/platform_def.h]. by [plat/common/aarch64/platform_mp_stack.S] and [plat/common/aarch64/platform_up_stack.S]. -* **#define : PCPU_DV_MEM_STACK_SIZE** - - Defines the coherent stack memory available to each CPU. This constant is used - by [plat/common/aarch64/platform_mp_stack.S] and - [plat/common/aarch64/platform_up_stack.S]. - * **#define : FIRMWARE_WELCOME_STR** Defines the character string printed by BL1 upon entry into the `bl1_main()` @@ -274,10 +269,18 @@ the following macro defined. In the ARM FVP port, this file is found in * **Macro : plat_print_gic_regs** This macro allows the crash reporting routine to print GIC registers - in case of an unhandled IRQ or FIQ in BL3-1. This aids in debugging and + in case of an unhandled exception in BL3-1. This aids in debugging and this macro can be defined to be empty in case GIC register reporting is not desired. +* **Macro : plat_print_interconnect_regs** + + This macro allows the crash reporting routine to print interconnect registers + in case of an unhandled exception in BL3-1. This aids in debugging and + this macro can be defined to be empty in case interconnect register reporting + is not desired. In the ARM FVP port, the CCI snoop control registers are + reported. + ### Other mandatory modifications The following mandatory modifications may be implemented in any file @@ -395,31 +398,6 @@ maximum of 4 CPUs: cluster_id = 8-bit value in MPIDR at affinity level 1 -### Function : platform_set_coherent_stack() - - Argument : unsigned long - Return : void - -A platform may need stack memory that is coherent with main memory to perform -certain operations like: - -* Turning the MMU on, or -* Flushing caches prior to powering down a CPU or cluster. - -Each BL stage allocates this coherent stack memory for each CPU in the -`tzfw_coherent_mem` section. - -This function sets the current stack pointer to the coherent stack that -has been allocated for the CPU specified by MPIDR. For BL images that only -require a stack for the primary CPU the parameter is ignored. The size of -the stack allocated to each CPU is specified by the platform defined constant -`PCPU_DV_MEM_STACK_SIZE`. - -Common implementations of this function for the UP and MP BL images are -provided in [plat/common/aarch64/platform_up_stack.S] and -[plat/common/aarch64/platform_mp_stack.S] - - ### Function : platform_is_primary_cpu() Argument : unsigned long @@ -1116,11 +1094,6 @@ the calling CPU is the last powered on CPU in the cluster, after powering down affinity level 0 (CPU), the platform port should power down affinity level 1 (the cluster) as well. -This function is called with coherent stacks. This allows the PSCI -implementation to flush caches at a given affinity level without running into -stale stack state after turning off the caches. On ARMv8-A cache hits do not -occur after the cache has been turned off. - #### plat_pm_ops.affinst_suspend() Perform the platform specific setup to power off an affinity instance in the @@ -1143,11 +1116,6 @@ case, the affinity instance is expected to save enough state so that it can resume execution by restoring this state when its powered on (see `affinst_suspend_finish()`). -This function is called with coherent stacks. This allows the PSCI -implementation to flush caches at a given affinity level without running into -stale stack state after turning off the caches. On ARMv8-A cache hits do not -occur after the cache has been turned off. - #### plat_pm_ops.affinst_on_finish() This function is called by the PSCI implementation after the calling CPU is @@ -1159,11 +1127,6 @@ services. The `MPIDR` (first argument), `affinity level` (second argument) and `state` (third argument) have a similar meaning as described in the previous operations. -This function is called with coherent stacks. This allows the PSCI -implementation to flush caches at a given affinity level without running into -stale stack state after turning off the caches. On ARMv8-A cache hits do not -occur after the cache has been turned off. - #### plat_pm_ops.affinst_on_suspend() This function is called by the PSCI implementation after the calling CPU is @@ -1176,11 +1139,6 @@ and also provide secure runtime firmware services. The `MPIDR` (first argument), `affinity level` (second argument) and `state` (third argument) have a similar meaning as described in the previous operations. -This function is called with coherent stacks. This allows the PSCI -implementation to flush caches at a given affinity level without running into -stale stack state after turning off the caches. On ARMv8-A cache hits do not -occur after the cache has been turned off. - BL3-1 platform initialization code must also detect the system topology and the state of each affinity instance in the topology. This information is critical for the PSCI runtime service to function correctly. More details are @@ -1316,6 +1274,41 @@ interrupts as Group1 interrupts. It reads the group value corresponding to the interrupt id from the relevant _Interrupt Group Register_ (`GICD_IGROUPRn`). It uses the group value to determine the type of interrupt. +3.5 Crash Reporting mechanism (in BL3-1) +---------------------------------------------- +BL3-1 implements a crash reporting mechanism which prints the various registers +of the CPU to enable quick crash analysis and debugging. It requires that a console +is designated as the crash console by the platform which will used to print the +register dump. + +The following functions must be implemented by the platform if it wants crash reporting +mechanism in BL3-1. The functions are implemented in assembly so that they can be +invoked without a C Runtime stack. + +### Function : plat_crash_console_init + + Argument : void + Return : int + +This API is used by the crash reporting mechanism to intialize the crash console. +It should only use the general purpose registers x0 to x2 to do the initiaization +and returns 1 on success. + +The FVP port designates the PL011_UART0 as the crash console and calls the +console_core_init() to initialize the console. + +### Function : plat_crash_console_putc + + Argument : int + Return : int + +This API is used by the crash reporting mechanism to print a character on the +designated crash console. It should only use general purpose registers x1 and +x2 to do its work. The parameter and the return value are in general purpose +register x0. + +The FVP port designates the PL011_UART0 as the crash console and calls the +console_core_putc() to print the character on the console. 4. C Library ------------- |