diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/arm/ccn/ccn.c | 97 | ||||
| -rw-r--r-- | drivers/arm/ccn/ccn_private.h | 19 | ||||
| -rw-r--r-- | drivers/arm/gic/common/gic_common.c | 13 | ||||
| -rw-r--r-- | drivers/arm/gic/common/gic_common_private.h | 104 | ||||
| -rw-r--r-- | drivers/arm/gic/gic_v2.c | 15 | ||||
| -rw-r--r-- | drivers/arm/gic/gic_v3.c | 4 | ||||
| -rw-r--r-- | drivers/arm/gic/v2/gicv2_helpers.c | 12 | ||||
| -rw-r--r-- | drivers/arm/gic/v2/gicv2_main.c | 3 | ||||
| -rw-r--r-- | drivers/arm/gic/v3/gicv3_helpers.c | 16 | ||||
| -rw-r--r-- | drivers/arm/gic/v3/gicv3_main.c | 3 | ||||
| -rw-r--r-- | drivers/arm/gic/v3/gicv3_private.h | 28 | ||||
| -rw-r--r-- | drivers/arm/pl011/pl011_console.S | 16 | ||||
| -rw-r--r-- | drivers/console/console.S | 2 |
13 files changed, 234 insertions, 98 deletions
diff --git a/drivers/arm/ccn/ccn.c b/drivers/arm/ccn/ccn.c index aef891b2..28d27098 100644 --- a/drivers/arm/ccn/ccn.c +++ b/drivers/arm/ccn/ccn.c @@ -268,7 +268,7 @@ static unsigned long long ccn_master_to_rn_id_map(unsigned long long master_map) /******************************************************************************* * This function executes the necessary operations to add or remove Request node * IDs specified in the 'rn_id_map' bitmap from the snoop/DVM domains specified - * in the 'hn_id_map'. The 'region_id' specifies the ID of the first HN-F/HN-I + * in the 'hn_id_map'. The 'region_id' specifies the ID of the first HN-F/MN * on which the operation should be performed. 'op_reg_offset' specifies the * type of operation (add/remove). 'stat_reg_offset' specifies the register * which should be polled to determine if the operation has completed or not. @@ -310,35 +310,6 @@ static void ccn_snoop_dvm_do_op(unsigned long long rn_id_map, } /******************************************************************************* - * This function reads the bitmap of Home nodes on the basis of the - * 'mn_hn_id_reg_offset' parameter from the Miscellaneous node's (MN) - * programmer's view. The MN has a register which carries the bitmap of present - * Home nodes of each type i.e. HN-Fs, HN-Is & HN-Ds. It calls - * 'ccn_snoop_dvm_do_op()' with this information to perform the actual - * operation. - ******************************************************************************/ -static void ccn_snoop_dvm_domain_common(unsigned long long rn_id_map, - unsigned int hn_op_reg_offset, - unsigned int hn_stat_reg_offset, - unsigned int mn_hn_id_reg_offset, - unsigned int hn_region_id) -{ - unsigned long long mn_hn_id_map; - - assert(ccn_plat_desc); - assert(ccn_plat_desc->periphbase); - - mn_hn_id_map = ccn_reg_read(ccn_plat_desc->periphbase, - MN_REGION_ID, - mn_hn_id_reg_offset); - ccn_snoop_dvm_do_op(rn_id_map, - mn_hn_id_map, - hn_region_id, - hn_op_reg_offset, - hn_stat_reg_offset); -} - -/******************************************************************************* * The following functions provide the boot and runtime API to the platform for * adding and removing master interfaces from the snoop/DVM domains. A bitmap of * master interfaces IDs is passed as a parameter. It is converted into a bitmap @@ -357,17 +328,18 @@ void ccn_enter_snoop_dvm_domain(unsigned long long master_iface_map) unsigned long long rn_id_map; rn_id_map = ccn_master_to_rn_id_map(master_iface_map); - ccn_snoop_dvm_domain_common(rn_id_map, - HNF_SDC_SET_OFFSET, - HNF_SDC_STAT_OFFSET, - MN_HNF_NODEID_OFFSET, - HNF_REGION_ID_START); - - ccn_snoop_dvm_domain_common(rn_id_map, - MN_DDC_SET_OFF, - MN_DDC_STAT_OFFSET, - MN_HNI_NODEID_OFFSET, - MN_REGION_ID); + ccn_snoop_dvm_do_op(rn_id_map, + CCN_GET_HN_NODEID_MAP(ccn_plat_desc->periphbase, + MN_HNF_NODEID_OFFSET), + HNF_REGION_ID_START, + HNF_SDC_SET_OFFSET, + HNF_SDC_STAT_OFFSET); + + ccn_snoop_dvm_do_op(rn_id_map, + CCN_GET_MN_NODEID_MAP(ccn_plat_desc->periphbase), + MN_REGION_ID, + MN_DDC_SET_OFFSET, + MN_DDC_STAT_OFFSET); } void ccn_exit_snoop_dvm_domain(unsigned long long master_iface_map) @@ -375,17 +347,18 @@ void ccn_exit_snoop_dvm_domain(unsigned long long master_iface_map) unsigned long long rn_id_map; rn_id_map = ccn_master_to_rn_id_map(master_iface_map); - ccn_snoop_dvm_domain_common(rn_id_map, - HNF_SDC_CLR_OFFSET, - HNF_SDC_STAT_OFFSET, - MN_HNF_NODEID_OFFSET, - HNF_REGION_ID_START); - - ccn_snoop_dvm_domain_common(rn_id_map, - MN_DDC_CLR_OFFSET, - MN_DDC_STAT_OFFSET, - MN_HNI_NODEID_OFFSET, - MN_REGION_ID); + ccn_snoop_dvm_do_op(rn_id_map, + CCN_GET_HN_NODEID_MAP(ccn_plat_desc->periphbase, + MN_HNF_NODEID_OFFSET), + HNF_REGION_ID_START, + HNF_SDC_CLR_OFFSET, + HNF_SDC_STAT_OFFSET); + + ccn_snoop_dvm_do_op(rn_id_map, + CCN_GET_MN_NODEID_MAP(ccn_plat_desc->periphbase), + MN_REGION_ID, + MN_DDC_CLR_OFFSET, + MN_DDC_STAT_OFFSET); } void ccn_enter_dvm_domain(unsigned long long master_iface_map) @@ -393,11 +366,11 @@ void ccn_enter_dvm_domain(unsigned long long master_iface_map) unsigned long long rn_id_map; rn_id_map = ccn_master_to_rn_id_map(master_iface_map); - ccn_snoop_dvm_domain_common(rn_id_map, - MN_DDC_SET_OFF, - MN_DDC_STAT_OFFSET, - MN_HNI_NODEID_OFFSET, - MN_REGION_ID); + ccn_snoop_dvm_do_op(rn_id_map, + CCN_GET_MN_NODEID_MAP(ccn_plat_desc->periphbase), + MN_REGION_ID, + MN_DDC_SET_OFFSET, + MN_DDC_STAT_OFFSET); } void ccn_exit_dvm_domain(unsigned long long master_iface_map) @@ -405,11 +378,11 @@ void ccn_exit_dvm_domain(unsigned long long master_iface_map) unsigned long long rn_id_map; rn_id_map = ccn_master_to_rn_id_map(master_iface_map); - ccn_snoop_dvm_domain_common(rn_id_map, - MN_DDC_CLR_OFFSET, - MN_DDC_STAT_OFFSET, - MN_HNI_NODEID_OFFSET, - MN_REGION_ID); + ccn_snoop_dvm_do_op(rn_id_map, + CCN_GET_MN_NODEID_MAP(ccn_plat_desc->periphbase), + MN_REGION_ID, + MN_DDC_CLR_OFFSET, + MN_DDC_STAT_OFFSET); } /******************************************************************************* diff --git a/drivers/arm/ccn/ccn_private.h b/drivers/arm/ccn/ccn_private.h index e92e8702..8b154725 100644 --- a/drivers/arm/ccn/ccn_private.h +++ b/drivers/arm/ccn/ccn_private.h @@ -147,7 +147,7 @@ typedef enum rn_types { #define MN_HNI_NODEID_OFFSET 0x01C0 #define MN_SN_NODEID_OFFSET 0x01D0 #define MN_DDC_STAT_OFFSET DOMAIN_CTRL_STAT_OFFSET -#define MN_DDC_SET_OFF DOMAIN_CTRL_SET_OFFSET +#define MN_DDC_SET_OFFSET DOMAIN_CTRL_SET_OFFSET #define MN_DDC_CLR_OFFSET DOMAIN_CTRL_CLR_OFFSET #define MN_ID_OFFSET REGION_ID_OFFSET @@ -236,4 +236,21 @@ static inline unsigned int count_set_bits(uint64_t bitmap) */ #define FOR_EACH_PRESENT_MASTER_INTERFACE(iface_id, bit_map) \ FOR_EACH_BIT(iface_id, bit_map) + +/* + * Macro that returns the node id bit map for the Miscellaneous Node + */ +#define CCN_GET_MN_NODEID_MAP(periphbase) \ + (1 << get_node_id(ccn_reg_read(periphbase, MN_REGION_ID, \ + REGION_ID_OFFSET))) + +/* + * This macro returns the bitmap of Home nodes on the basis of the + * 'mn_hn_id_reg_offset' parameter from the Miscellaneous node's (MN) + * programmer's view. The MN has a register which carries the bitmap of present + * Home nodes of each type i.e. HN-Fs, HN-Is & HN-Ds. + */ +#define CCN_GET_HN_NODEID_MAP(periphbase, mn_hn_id_reg_offset) \ + ccn_reg_read(periphbase, MN_REGION_ID, mn_hn_id_reg_offset) + #endif /* __CCN_PRIVATE_H__ */ diff --git a/drivers/arm/gic/common/gic_common.c b/drivers/arm/gic/common/gic_common.c index 17be61d5..cfa0d23e 100644 --- a/drivers/arm/gic/common/gic_common.c +++ b/drivers/arm/gic/common/gic_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -31,6 +31,7 @@ #include <assert.h> #include <gic_common.h> #include <mmio.h> +#include "gic_common_private.h" /******************************************************************************* * GIC Distributor interface accessors for reading entire registers @@ -239,7 +240,10 @@ void gicd_write_nsacr(uintptr_t base, unsigned int id, unsigned int val) } /******************************************************************************* - * GIC Distributor interface accessors for individual interrupt manipulation + * GIC Distributor functions for accessing the GIC registers + * corresponding to a single interrupt ID. These functions use bitwise + * operations or appropriate register accesses to modify or return + * the bit-field corresponding the single interrupt ID. ******************************************************************************/ unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id) { @@ -306,3 +310,8 @@ void gicd_set_icactiver(uintptr_t base, unsigned int id) gicd_write_icactiver(base, id, (1 << bit_num)); } + +void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri) +{ + mmio_write_8(base + GICD_IPRIORITYR + id, pri & GIC_PRI_MASK); +} diff --git a/drivers/arm/gic/common/gic_common_private.h b/drivers/arm/gic/common/gic_common_private.h new file mode 100644 index 00000000..2919b7f8 --- /dev/null +++ b/drivers/arm/gic/common/gic_common_private.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef GIC_COMMON_PRIVATE_H_ +#define GIC_COMMON_PRIVATE_H_ + +#include <gic_common.h> +#include <mmio.h> +#include <stdint.h> + +/******************************************************************************* + * GIC Distributor interface register accessors that are common to GICv3 & GICv2 + ******************************************************************************/ +static inline unsigned int gicd_read_ctlr(uintptr_t base) +{ + return mmio_read_32(base + GICD_CTLR); +} + +static inline unsigned int gicd_read_typer(uintptr_t base) +{ + return mmio_read_32(base + GICD_TYPER); +} + +static inline unsigned int gicd_read_iidr(uintptr_t base) +{ + return mmio_read_32(base + GICD_IIDR); +} + +static inline void gicd_write_ctlr(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICD_CTLR, val); +} + +/******************************************************************************* + * GIC Distributor function prototypes for accessing entire registers. + * Note: The raw register values correspond to multiple interrupt IDs and + * the number of interrupt IDs involved depends on the register accessed. + ******************************************************************************/ +unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id); +unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id); +unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id); +unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id); +unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id); +unsigned int gicd_read_isactiver(uintptr_t base, unsigned int id); +unsigned int gicd_read_icactiver(uintptr_t base, unsigned int id); +unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int id); +unsigned int gicd_read_icfgr(uintptr_t base, unsigned int id); +unsigned int gicd_read_nsacr(uintptr_t base, unsigned int id); +void gicd_write_igroupr(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_isenabler(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_icenabler(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_ispendr(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_icpendr(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_isactiver(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_icactiver(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_icfgr(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_nsacr(uintptr_t base, unsigned int id, unsigned int val); + +/******************************************************************************* + * GIC Distributor function prototypes for accessing the GIC registers + * corresponding to a single interrupt ID. These functions use bitwise + * operations or appropriate register accesses to modify or return + * the bit-field corresponding the single interrupt ID. + ******************************************************************************/ +unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id); +void gicd_set_igroupr(uintptr_t base, unsigned int id); +void gicd_clr_igroupr(uintptr_t base, unsigned int id); +void gicd_set_isenabler(uintptr_t base, unsigned int id); +void gicd_set_icenabler(uintptr_t base, unsigned int id); +void gicd_set_ispendr(uintptr_t base, unsigned int id); +void gicd_set_icpendr(uintptr_t base, unsigned int id); +void gicd_set_isactiver(uintptr_t base, unsigned int id); +void gicd_set_icactiver(uintptr_t base, unsigned int id); +void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri); + +#endif /* GIC_COMMON_PRIVATE_H_ */ diff --git a/drivers/arm/gic/gic_v2.c b/drivers/arm/gic/gic_v2.c index dc5dc08c..05399c3a 100644 --- a/drivers/arm/gic/gic_v2.c +++ b/drivers/arm/gic/gic_v2.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -261,10 +261,6 @@ void gicd_set_icactiver(uintptr_t base, unsigned int id) */ void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri) { - unsigned int reg = base + GICD_IPRIORITYR + (id & ~3); - unsigned int shift = (id & 3) << 3; - unsigned int reg_val = mmio_read_32(reg); - /* * Enforce ARM recommendation to manage priority values such * that group1 interrupts always have a lower priority than @@ -278,17 +274,12 @@ void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri) pri >= GIC_HIGHEST_SEC_PRIORITY && pri <= GIC_LOWEST_SEC_PRIORITY); - reg_val &= ~(GIC_PRI_MASK << shift); - reg_val |= (pri & GIC_PRI_MASK) << shift; - mmio_write_32(reg, reg_val); + mmio_write_8(base + GICD_IPRIORITYR + id, pri & GIC_PRI_MASK); } void gicd_set_itargetsr(uintptr_t base, unsigned int id, unsigned int target) { - unsigned byte_off = id & ((1 << ITARGETSR_SHIFT) - 1); - unsigned int reg_val = gicd_read_itargetsr(base, id); - - gicd_write_itargetsr(base, id, reg_val | (target << (byte_off << 3))); + mmio_write_8(base + GICD_ITARGETSR + id, target & GIC_TARGET_CPU_MASK); } /******************************************************************************* diff --git a/drivers/arm/gic/gic_v3.c b/drivers/arm/gic/gic_v3.c index f4296629..11185b2e 100644 --- a/drivers/arm/gic/gic_v3.c +++ b/drivers/arm/gic/gic_v3.c @@ -60,8 +60,8 @@ uintptr_t gicv3_get_rdist(uintptr_t gicr_base, uint64_t mpidr) /* Disable this print for now as it appears every time * when using PSCI CPU_SUSPEND. * TODO: Print this only the first time for each CPU. - * INFO("GICv3 - Found RDIST for MPIDR(0x%lx) at 0x%lx\n", - * mpidr, addr); + * INFO("GICv3 - Found RDIST for MPIDR(0x%lx) at %p\n", + * mpidr, (void *) addr); */ return addr; } diff --git a/drivers/arm/gic/v2/gicv2_helpers.c b/drivers/arm/gic/v2/gicv2_helpers.c index 1f904c51..b60a5cd9 100644 --- a/drivers/arm/gic/v2/gicv2_helpers.c +++ b/drivers/arm/gic/v2/gicv2_helpers.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -33,6 +33,7 @@ #include <assert.h> #include <debug.h> #include <gic_common.h> +#include "../common/gic_common_private.h" #include "gicv2_private.h" /* @@ -101,10 +102,7 @@ void gicd_write_spendsgir(uintptr_t base, unsigned int id, unsigned int val) */ void gicd_set_itargetsr(uintptr_t base, unsigned int id, unsigned int target) { - unsigned byte_off = id & ((1 << ITARGETSR_SHIFT) - 1); - unsigned int reg_val = gicd_read_itargetsr(base, id); - - gicd_write_itargetsr(base, id, reg_val | (target << (byte_off << 3))); + mmio_write_8(base + GICD_ITARGETSR + id, target & GIC_TARGET_CPU_MASK); } /******************************************************************************* @@ -166,7 +164,7 @@ void gicv2_secure_spis_configure(uintptr_t gicd_base, gicd_clr_igroupr(gicd_base, irq_num); /* Set the priority of this interrupt */ - gicd_write_ipriorityr(gicd_base, + gicd_set_ipriorityr(gicd_base, irq_num, GIC_HIGHEST_SEC_PRIORITY); @@ -213,7 +211,7 @@ void gicv2_secure_ppi_sgi_setup(uintptr_t gicd_base, sec_ppi_sgi_mask |= 1U << irq_num; /* Set the priority of this interrupt */ - gicd_write_ipriorityr(gicd_base, + gicd_set_ipriorityr(gicd_base, irq_num, GIC_HIGHEST_SEC_PRIORITY); } diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c index cf939261..305a8b07 100644 --- a/drivers/arm/gic/v2/gicv2_main.c +++ b/drivers/arm/gic/v2/gicv2_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -34,6 +34,7 @@ #include <debug.h> #include <gic_common.h> #include <gicv2.h> +#include "../common/gic_common_private.h" #include "gicv2_private.h" static const gicv2_driver_data_t *driver_data; diff --git a/drivers/arm/gic/v3/gicv3_helpers.c b/drivers/arm/gic/v3/gicv3_helpers.c index 2fb98cbb..07ae54c4 100644 --- a/drivers/arm/gic/v3/gicv3_helpers.c +++ b/drivers/arm/gic/v3/gicv3_helpers.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -33,6 +33,7 @@ #include <assert.h> #include <debug.h> #include <gic_common.h> +#include "../common/gic_common_private.h" #include "gicv3_private.h" /* @@ -194,6 +195,15 @@ void gicr_set_isenabler0(uintptr_t base, unsigned int id) gicr_write_isenabler0(base, (1 << bit_num)); } +/* + * Accessor to set the byte corresponding to interrupt ID + * in GIC Re-distributor IPRIORITYR. + */ +void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri) +{ + mmio_write_8(base + GICR_IPRIORITYR + id, pri & GIC_PRI_MASK); +} + /****************************************************************************** * This function marks the core as awake in the re-distributor and * ensures that the interface is active. @@ -330,7 +340,7 @@ void gicv3_secure_spis_configure(uintptr_t gicd_base, gicd_clr_igrpmodr(gicd_base, irq_num); /* Set the priority of this interrupt */ - gicd_write_ipriorityr(gicd_base, + gicd_set_ipriorityr(gicd_base, irq_num, GIC_HIGHEST_SEC_PRIORITY); @@ -404,7 +414,7 @@ void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base, gicr_clr_igrpmodr0(gicr_base, irq_num); /* Set the priority of this interrupt */ - gicr_write_ipriorityr(gicr_base, + gicr_set_ipriorityr(gicr_base, irq_num, GIC_HIGHEST_SEC_PRIORITY); diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c index d5cd0ed9..6c6c7af9 100644 --- a/drivers/arm/gic/v3/gicv3_main.c +++ b/drivers/arm/gic/v3/gicv3_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -34,6 +34,7 @@ #include <debug.h> #include <gic_common.h> #include <gicv3.h> +#include "../common/gic_common_private.h" #include "gicv3_private.h" static const gicv3_driver_data_t *driver_data; diff --git a/drivers/arm/gic/v3/gicv3_private.h b/drivers/arm/gic/v3/gicv3_private.h index c8b311a1..5e2409fc 100644 --- a/drivers/arm/gic/v3/gicv3_private.h +++ b/drivers/arm/gic/v3/gicv3_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -84,16 +84,24 @@ ((typer_val >> 32) & 0xffffff)) /******************************************************************************* - * Private function prototypes + * Private GICv3 function prototypes for accessing entire registers. + * Note: The raw register values correspond to multiple interrupt IDs and + * the number of interrupt IDs involved depends on the register accessed. ******************************************************************************/ unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id); unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id); +void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val); +void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val); + +/******************************************************************************* + * Private GICv3 function prototypes for accessing the GIC registers + * corresponding to a single interrupt ID. These functions use bitwise + * operations or appropriate register accesses to modify or return + * the bit-field corresponding the single interrupt ID. + ******************************************************************************/ unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id); unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id); unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id); -unsigned int gicv3_get_pending_grp1_interrupt_id(unsigned int pending_grp); -void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val); -void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val); void gicd_set_igrpmodr(uintptr_t base, unsigned int id); void gicr_set_igrpmodr0(uintptr_t base, unsigned int id); void gicr_set_isenabler0(uintptr_t base, unsigned int id); @@ -101,6 +109,11 @@ void gicr_set_igroupr0(uintptr_t base, unsigned int id); void gicd_clr_igrpmodr(uintptr_t base, unsigned int id); void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id); void gicr_clr_igroupr0(uintptr_t base, unsigned int id); +void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri); + +/******************************************************************************* + * Private GICv3 helper function prototypes + ******************************************************************************/ void gicv3_spis_configure_defaults(uintptr_t gicd_base); void gicv3_ppi_sgi_configure_defaults(uintptr_t gicr_base); void gicv3_secure_spis_configure(uintptr_t gicd_base, @@ -179,6 +192,11 @@ static inline void gicr_write_waker(uintptr_t base, unsigned int val) mmio_write_32(base + GICR_WAKER, val); } +/******************************************************************************* + * GIC Re-distributor functions for accessing entire registers. + * Note: The raw register values correspond to multiple interrupt IDs and + * the number of interrupt IDs involved depends on the register accessed. + ******************************************************************************/ static inline unsigned int gicr_read_icenabler0(uintptr_t base) { return mmio_read_32(base + GICR_ICENABLER0); diff --git a/drivers/arm/pl011/pl011_console.S b/drivers/arm/pl011/pl011_console.S index 47608da3..f29f895b 100644 --- a/drivers/arm/pl011/pl011_console.S +++ b/drivers/arm/pl011/pl011_console.S @@ -54,7 +54,7 @@ * w1 - Uart clock in Hz * w2 - Baud rate * Out: return 1 on success else 0 on error - * Clobber list : x1, x2 + * Clobber list : x1, x2, x3, x4 * ----------------------------------------------- */ func console_core_init @@ -64,6 +64,20 @@ func console_core_init /* Check baud rate and uart clock for sanity */ cbz w1, core_init_fail cbz w2, core_init_fail + /* Disable uart before programming */ + ldr w3, [x0, #UARTCR] + mov w4, #PL011_UARTCR_UARTEN + bic w3, w3, w4 + str w3, [x0, #UARTCR] + /* Flush the transmit FIFO */ + ldr w3, [x0, #UARTLCR_H] + mov w4, #PL011_UARTLCR_H_FEN + bic w3, w3, w4 + str w3, [x0, #UARTLCR_H] + /* Wait for the end of Tx of current character */ +busy_loop: + ldr w3, [x0, #UARTFR] + tbnz w3, #PL011_UARTFR_BUSY_BIT, busy_loop /* Program the baudrate */ /* Divisor = (Uart clock * 4) / baudrate */ lsl w1, w1, #2 diff --git a/drivers/console/console.S b/drivers/console/console.S index b7723638..797b5645 100644 --- a/drivers/console/console.S +++ b/drivers/console/console.S @@ -54,7 +54,7 @@ * w1 - Uart clock in Hz * w2 - Baud rate * out: return 1 on success else 0 on error - * Clobber list : x1 - x3 + * Clobber list : x1 - x4 * ----------------------------------------------- */ func console_init |