diff options
Diffstat (limited to 'include/common')
| -rw-r--r-- | include/common/asm_macros.S | 35 | ||||
| -rw-r--r-- | include/common/auth.h | 88 | ||||
| -rw-r--r-- | include/common/bl_common.h | 27 | ||||
| -rw-r--r-- | include/common/el3_common_macros.S | 256 | ||||
| -rw-r--r-- | include/common/tbbr/cot_def.h | 38 | ||||
| -rw-r--r-- | include/common/tbbr/tbbr_img_def.h | 66 |
6 files changed, 370 insertions, 140 deletions
diff --git a/include/common/asm_macros.S b/include/common/asm_macros.S index f9e7823c..45058a60 100644 --- a/include/common/asm_macros.S +++ b/include/common/asm_macros.S @@ -99,41 +99,6 @@ .size \_name, . - \_name .endm - /* --------------------------------------------- - * Find the type of reset and jump to handler - * if present. If the handler is null then it is - * a cold boot. The primary cpu will set up the - * platform while the secondaries wait for - * their turn to be woken up - * --------------------------------------------- - */ - .macro wait_for_entrypoint -wait_for_entrypoint: - mrs x0, mpidr_el1 - bl platform_get_entrypoint - cbnz x0, do_warm_boot - mrs x0, mpidr_el1 - bl platform_is_primary_cpu - cbnz x0, do_cold_boot - - /* --------------------------------------------- - * Perform any platform specific secondary cpu - * actions - * --------------------------------------------- - */ - bl plat_secondary_cold_boot_setup - b wait_for_entrypoint - - do_warm_boot: - /* --------------------------------------------- - * Jump to BL31 for all warm boot init. - * --------------------------------------------- - */ - blr x0 - - do_cold_boot: - .endm - /* * This macro declares an array of 1 or more stacks, properly * aligned and in the requested section diff --git a/include/common/auth.h b/include/common/auth.h deleted file mode 100644 index 3c3a6bd0..00000000 --- a/include/common/auth.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef AUTH_H_ -#define AUTH_H_ - -#include <stddef.h> -#include <stdint.h> - -/* - * Authentication infrastructure for Trusted Boot - * - * This infrastructure provides an API to access the authentication module. This - * module will implement the required operations for Trusted Boot by creating an - * instance of the structure 'auth_mod_t'. This instance must be called - * 'auth_mod' and must provide the functions to initialize the module and - * verify the authenticity of the images. - */ - -/* Objects (images and certificates) involved in the TBB process */ -enum { - AUTH_BL2_IMG_CERT, - AUTH_BL2_IMG, - AUTH_TRUSTED_KEY_CERT, - AUTH_BL30_KEY_CERT, - AUTH_BL30_IMG_CERT, - AUTH_BL30_IMG, - AUTH_BL31_KEY_CERT, - AUTH_BL31_IMG_CERT, - AUTH_BL31_IMG, - AUTH_BL32_KEY_CERT, - AUTH_BL32_IMG_CERT, - AUTH_BL32_IMG, - AUTH_BL33_KEY_CERT, - AUTH_BL33_IMG_CERT, - AUTH_BL33_IMG, - AUTH_NUM_OBJ -}; - -/* Authentication module structure */ -typedef struct auth_mod_s { - /* [mandatory] Module name. Printed to the log during initialization */ - const char *name; - - /* [mandatory] Initialize the authentication module */ - int (*init)(void); - - /* [mandatory] This function will be called to authenticate a new - * object loaded into memory. The obj_id corresponds to one of the - * values in the enumeration above */ - int (*verify)(unsigned int obj_id, uintptr_t obj_buf, size_t len); -} auth_mod_t; - -/* This variable must be instantiated by the authentication module */ -extern const auth_mod_t auth_mod; - -/* Public functions */ -void auth_init(void); -int auth_verify_obj(unsigned int obj_id, uintptr_t obj_buf, size_t len); - -#endif /* AUTH_H_ */ diff --git a/include/common/bl_common.h b/include/common/bl_common.h index 33b75f18..b1a9c8f6 100644 --- a/include/common/bl_common.h +++ b/include/common/bl_common.h @@ -90,18 +90,6 @@ (_p)->h.attr = (uint32_t)(_attr) ; \ } while (0) -/******************************************************************************* - * Constant that indicates if this is the first version of the reset handler - * contained in an image. This will be the case when the image is BL1 or when - * its BL3-1 and RESET_TO_BL31 is true. This constant enables a subsequent - * version of the reset handler to perform actions that override the ones - * performed in the first version of the code. This will be required when the - * first version exists in an un-modifiable image e.g. a BootROM image. - ******************************************************************************/ -#if IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31) -#define FIRST_RESET_HANDLER_CALL -#endif - #ifndef __ASSEMBLY__ #include <cdefs.h> /* For __dead2 */ #include <cassert.h> @@ -195,9 +183,9 @@ typedef struct image_info { * This structure represents the superset of information that can be passed to * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be * populated only if BL2 detects its presence. A pointer to a structure of this - * type should be passed in X3 to BL31's cold boot entrypoint + * type should be passed in X0 to BL3-1's cold boot entrypoint. * - * Use of this structure and the X3 parameter is not mandatory: the BL3-1 + * Use of this structure and the X0 parameter is not mandatory: the BL3-1 * platform code can use other mechanisms to provide the necessary information * about BL3-2 and BL3-3 to the common and SPD code. * @@ -238,12 +226,17 @@ CASSERT(sizeof(unsigned long) == ******************************************************************************/ unsigned long page_align(unsigned long, unsigned); void change_security_state(unsigned int); -unsigned long image_size(const char *); +unsigned long image_size(unsigned int image_id); int load_image(meminfo_t *mem_layout, - const char *image_name, - uint64_t image_base, + unsigned int image_id, + uintptr_t image_base, image_info_t *image_data, entry_point_info_t *entry_point_info); +int load_auth_image(meminfo_t *mem_layout, + unsigned int image_name, + uintptr_t image_base, + image_info_t *image_data, + entry_point_info_t *entry_point_info); extern const char build_message[]; extern const char version_string[]; diff --git a/include/common/el3_common_macros.S b/include/common/el3_common_macros.S new file mode 100644 index 00000000..eb033a6e --- /dev/null +++ b/include/common/el3_common_macros.S @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __EL3_COMMON_MACROS_S__ +#define __EL3_COMMON_MACROS_S__ + +#include <arch.h> +#include <asm_macros.S> + + /* + * Helper macro to initialise EL3 registers we care about. + */ + .macro el3_arch_init_common _exception_vectors + /* --------------------------------------------------------------------- + * Enable the instruction cache, stack pointer and data access alignment + * checks + * --------------------------------------------------------------------- + */ + mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) + mrs x0, sctlr_el3 + orr x0, x0, x1 + msr sctlr_el3, x0 + isb + +#if IMAGE_BL31 + /* --------------------------------------------------------------------- + * Initialise the per-cpu cache pointer to the CPU. + * This is done early to enable crash reporting to have access to crash + * stack. Since crash reporting depends on cpu_data to report the + * unhandled exception, not doing so can lead to recursive exceptions + * due to a NULL TPIDR_EL3. + * --------------------------------------------------------------------- + */ + bl init_cpu_data_ptr +#endif /* IMAGE_BL31 */ + + /* --------------------------------------------------------------------- + * Set the exception vectors. + * --------------------------------------------------------------------- + */ + adr x0, \_exception_vectors + msr vbar_el3, x0 + isb + + /* --------------------------------------------------------------------- + * Enable the SError interrupt now that the exception vectors have been + * setup. + * --------------------------------------------------------------------- + */ + msr daifclr, #DAIF_ABT_BIT + + /* --------------------------------------------------------------------- + * The initial state of the Architectural feature trap register + * (CPTR_EL3) is unknown and it must be set to a known state. All + * feature traps are disabled. Some bits in this register are marked as + * reserved and should not be modified. + * + * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 + * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. + * + * CPTR_EL3.TTA: This causes access to the Trace functionality to trap + * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register + * access to trace functionality is not supported, this bit is RES0. + * + * CPTR_EL3.TFP: This causes instructions that access the registers + * associated with Floating Point and Advanced SIMD execution to trap + * to EL3 when executed from any exception level, unless trapped to EL1 + * or EL2. + * --------------------------------------------------------------------- + */ + mrs x0, cptr_el3 + bic w0, w0, #TCPAC_BIT + bic w0, w0, #TTA_BIT + bic w0, w0, #TFP_BIT + msr cptr_el3, x0 + .endm + +/* ----------------------------------------------------------------------------- + * This is the super set of actions that need to be performed during a cold boot + * or a warm boot in EL3. This code is shared by BL1 and BL3-1. + * + * This macro will always perform reset handling, architectural initialisations + * and stack setup. The rest of the actions are optional because they might not + * be needed, depending on the context in which this macro is called. This is + * why this macro is parameterised ; each parameter allows to enable/disable + * some actions. + * + * _set_endian: + * Whether the macro needs to configure the endianness of data accesses. + * + * _warm_boot_mailbox: + * Whether the macro needs to detect the type of boot (cold/warm). The + * detection is based on the platform entrypoint address : if it is zero + * then it is a cold boot, otherwise it is a warm boot. In the latter case, + * this macro jumps on the platform entrypoint address. + * + * _secondary_cold_boot: + * Whether the macro needs to identify the CPU that is calling it: primary + * CPU or secondary CPU. The primary CPU will be allowed to carry on with + * the platform initialisations, while the secondaries will be put in a + * platform-specific state in the meantime. + * + * If the caller knows this macro will only be called by the primary CPU + * then this parameter can be defined to 0 to skip this step. + * + * _init_memory: + * Whether the macro needs to initialise the memory. + * + * _init_c_runtime: + * Whether the macro needs to initialise the C runtime environment. + * + * _exception_vectors: + * Address of the exception vectors to program in the VBAR_EL3 register. + * ----------------------------------------------------------------------------- + */ + .macro el3_entrypoint_common \ + _set_endian, _warm_boot_mailbox, _secondary_cold_boot, \ + _init_memory, _init_c_runtime, _exception_vectors + + .if \_set_endian + /* ------------------------------------------------------------- + * Set the CPU endianness before doing anything that might + * involve memory reads or writes. + * ------------------------------------------------------------- + */ + mrs x0, sctlr_el3 + bic x0, x0, #SCTLR_EE_BIT + msr sctlr_el3, x0 + isb + .endif /* _set_endian */ + + .if \_warm_boot_mailbox + /* ------------------------------------------------------------- + * This code will be executed for both warm and cold resets. + * Now is the time to distinguish between the two. + * Query the platform entrypoint address and if it is not zero + * then it means it is a warm boot so jump to this address. + * ------------------------------------------------------------- + */ + mrs x0, mpidr_el1 + bl platform_get_entrypoint + cbz x0, do_cold_boot + br x0 + + do_cold_boot: + .endif /* _warm_boot_mailbox */ + + .if \_secondary_cold_boot + /* ------------------------------------------------------------- + * It is a cold boot. + * The primary CPU will set up the platform while the + * secondaries are placed in a platform-specific state until the + * primary CPU performs the necessary actions to bring them out + * of that state and allows entry into the OS. + * ------------------------------------------------------------- + */ + mrs x0, mpidr_el1 + bl platform_is_primary_cpu + cbnz x0, do_primary_cold_boot + + /* This is a cold boot on a secondary CPU */ + bl plat_secondary_cold_boot_setup + /* plat_secondary_cold_boot_setup() is not supposed to return */ + secondary_panic: + b secondary_panic + + do_primary_cold_boot: + .endif /* _secondary_cold_boot */ + + /* --------------------------------------------------------------------- + * Perform any processor specific actions upon reset e.g. cache, TLB + * invalidations etc. + * --------------------------------------------------------------------- + */ + bl reset_handler + + el3_arch_init_common \_exception_vectors + + .if \_init_memory + bl platform_mem_init + .endif /* _init_memory */ + + /* --------------------------------------------------------------------- + * Init C runtime environment: + * - Zero-initialise the NOBITS sections. There are 2 of them: + * - the .bss section; + * - the coherent memory section (if any). + * - Relocate the data section from ROM to RAM, if required. + * --------------------------------------------------------------------- + */ + .if \_init_c_runtime + ldr x0, =__BSS_START__ + ldr x1, =__BSS_SIZE__ + bl zeromem16 + +#if USE_COHERENT_MEM + ldr x0, =__COHERENT_RAM_START__ + ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ + bl zeromem16 +#endif + +#if IMAGE_BL1 + ldr x0, =__DATA_RAM_START__ + ldr x1, =__DATA_ROM_START__ + ldr x2, =__DATA_SIZE__ + bl memcpy16 +#endif + .endif /* _init_c_runtime */ + +#if IMAGE_BL31 + /* --------------------------------------------------------------------- + * Use SP_EL0 for the C runtime stack. + * --------------------------------------------------------------------- + */ + msr spsel, #0 +#endif /* IMAGE_BL31 */ + + /* --------------------------------------------------------------------- + * Allocate a stack whose memory will be marked as Normal-IS-WBWA when + * the MMU is enabled. There is no risk of reading stale stack memory + * after enabling the MMU as only the primary CPU is running at the + * moment. + * --------------------------------------------------------------------- + */ + mrs x0, mpidr_el1 + bl platform_set_stack + .endm + +#endif /* __EL3_COMMON_MACROS_S__ */ diff --git a/include/common/tbbr/cot_def.h b/include/common/tbbr/cot_def.h new file mode 100644 index 00000000..d6dca4ae --- /dev/null +++ b/include/common/tbbr/cot_def.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __COT_DEF_H__ +#define __COT_DEF_H__ + +/* TBBR CoT definitions */ + +#define COT_MAX_VERIFIED_PARAMS 4 + +#endif /* __COT_DEF_H__ */ diff --git a/include/common/tbbr/tbbr_img_def.h b/include/common/tbbr/tbbr_img_def.h new file mode 100644 index 00000000..c43c3954 --- /dev/null +++ b/include/common/tbbr/tbbr_img_def.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TBBR_IMG_DEF_H__ +#define __TBBR_IMG_DEF_H__ + +/* Firmware Image Package */ +#define FIP_IMAGE_ID 0 + +/* Trusted Boot Firmware BL2 */ +#define BL2_IMAGE_ID 1 + +/* SCP Firmware BL3-0 */ +#define BL30_IMAGE_ID 2 + +/* EL3 Runtime Firmware BL31 */ +#define BL31_IMAGE_ID 3 + +/* Secure Payload BL32 (Trusted OS) */ +#define BL32_IMAGE_ID 4 + +/* Non-Trusted Firmware BL33 */ +#define BL33_IMAGE_ID 5 + +/* Certificates */ +#define BL2_CERT_ID 6 +#define TRUSTED_KEY_CERT_ID 7 + +#define BL30_KEY_CERT_ID 8 +#define BL31_KEY_CERT_ID 9 +#define BL32_KEY_CERT_ID 10 +#define BL33_KEY_CERT_ID 11 + +#define BL30_CERT_ID 12 +#define BL31_CERT_ID 13 +#define BL32_CERT_ID 14 +#define BL33_CERT_ID 15 + +#endif /* __TBBR_IMG_DEF_H__ */ |