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-rw-r--r--include/lib/bakery_lock.h3
-rw-r--r--include/lib/cassert.h2
-rw-r--r--include/lib/cpus/aarch64/cortex_a57.h7
3 files changed, 6 insertions, 6 deletions
diff --git a/include/lib/bakery_lock.h b/include/lib/bakery_lock.h
index 86adb9cb..8a538917 100644
--- a/include/lib/bakery_lock.h
+++ b/include/lib/bakery_lock.h
@@ -100,8 +100,7 @@ inline void bakery_lock_init(bakery_lock_t *bakery) {}
void bakery_lock_get(bakery_lock_t *bakery);
void bakery_lock_release(bakery_lock_t *bakery);
-#define DEFINE_BAKERY_LOCK(_name) bakery_lock_t _name \
- __attribute__ ((section("bakery_lock")))
+#define DEFINE_BAKERY_LOCK(_name) bakery_lock_t _name __section("bakery_lock")
#define DECLARE_BAKERY_LOCK(_name) extern bakery_lock_t _name
diff --git a/include/lib/cassert.h b/include/lib/cassert.h
index e8089cbb..00ee4d59 100644
--- a/include/lib/cassert.h
+++ b/include/lib/cassert.h
@@ -40,6 +40,6 @@
* compiler warning.
******************************************************************************/
#define CASSERT(cond, msg) \
- typedef char msg[(cond) ? 1 : -1] __attribute__((unused))
+ typedef char msg[(cond) ? 1 : -1] __unused
#endif /* __CASSERT_H__ */
diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h
index c81259c8..c512129a 100644
--- a/include/lib/cpus/aarch64/cortex_a57.h
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -61,8 +61,9 @@
******************************************************************************/
#define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */
-#define CPUACTLR_NO_ALLOC_WBWA (1 << 49)
-#define CPUACTLR_DCC_AS_DCCI (1 << 44)
+#define CPUACTLR_DIS_OVERREAD (1 << 52)
+#define CPUACTLR_NO_ALLOC_WBWA (1 << 49)
+#define CPUACTLR_DCC_AS_DCCI (1 << 44)
/*******************************************************************************
* L2 Control register specific definitions.