diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/common/asm_macros.S | 4 | ||||
| -rw-r--r-- | include/drivers/arm/arm_gic.h | 23 | ||||
| -rw-r--r-- | include/drivers/arm/gic_common.h | 173 | ||||
| -rw-r--r-- | include/drivers/arm/gic_v2.h | 7 | ||||
| -rw-r--r-- | include/drivers/arm/gic_v3.h | 8 | ||||
| -rw-r--r-- | include/drivers/arm/gicv2.h | 165 | ||||
| -rw-r--r-- | include/drivers/arm/gicv3.h | 266 | ||||
| -rw-r--r-- | include/drivers/arm/sp805.h | 58 | ||||
| -rw-r--r-- | include/drivers/arm/tzc400.h | 4 | ||||
| -rw-r--r-- | include/lib/aarch64/arch.h | 12 | ||||
| -rw-r--r-- | include/lib/aarch64/arch_helpers.h | 18 | ||||
| -rw-r--r-- | include/plat/arm/board/common/board_arm_oid.h | 145 | ||||
| -rw-r--r-- | include/plat/arm/board/common/drivers/norflash.h | 68 | ||||
| -rw-r--r-- | include/plat/arm/board/common/v2m_def.h | 9 | ||||
| -rw-r--r-- | include/plat/arm/common/arm_def.h | 9 | ||||
| -rw-r--r-- | include/plat/arm/common/plat_arm.h | 1 | ||||
| -rw-r--r-- | include/plat/common/common_def.h | 9 |
17 files changed, 931 insertions, 48 deletions
diff --git a/include/common/asm_macros.S b/include/common/asm_macros.S index 128259f1..a331c051 100644 --- a/include/common/asm_macros.S +++ b/include/common/asm_macros.S @@ -101,10 +101,10 @@ /* * Theses macros are used to create function labels for deprecated - * APIs. If WARN_DEPRECATED is non zero, the callers of these APIs + * APIs. If ERROR_DEPRECATED is non zero, the callers of these APIs * will fail to link and cause build failure. */ -#if WARN_DEPRECATED +#if ERROR_DEPRECATED .macro func_deprecated _name func deprecated\_name .endm diff --git a/include/drivers/arm/arm_gic.h b/include/drivers/arm/arm_gic.h index 5752d8f9..8c1f03fb 100644 --- a/include/drivers/arm/arm_gic.h +++ b/include/drivers/arm/arm_gic.h @@ -31,6 +31,7 @@ #ifndef __ARM_GIC_H__ #define __ARM_GIC_H__ +#include <common_def.h> #include <stdint.h> /******************************************************************************* @@ -40,18 +41,18 @@ void arm_gic_init(uintptr_t gicc_base, uintptr_t gicd_base, uintptr_t gicr_base, const unsigned int *irq_sec_ptr, - unsigned int num_irqs); -void arm_gic_setup(void); -void arm_gic_cpuif_deactivate(void); -void arm_gic_cpuif_setup(void); -void arm_gic_pcpu_distif_setup(void); + unsigned int num_irqs) __warn_deprecated; +void arm_gic_setup(void) __warn_deprecated; +void arm_gic_cpuif_deactivate(void) __warn_deprecated; +void arm_gic_cpuif_setup(void) __warn_deprecated; +void arm_gic_pcpu_distif_setup(void) __warn_deprecated; uint32_t arm_gic_interrupt_type_to_line(uint32_t type, - uint32_t security_state); -uint32_t arm_gic_get_pending_interrupt_type(void); -uint32_t arm_gic_get_pending_interrupt_id(void); -uint32_t arm_gic_acknowledge_interrupt(void); -void arm_gic_end_of_interrupt(uint32_t id); -uint32_t arm_gic_get_interrupt_type(uint32_t id); + uint32_t security_state) __warn_deprecated; +uint32_t arm_gic_get_pending_interrupt_type(void) __warn_deprecated; +uint32_t arm_gic_get_pending_interrupt_id(void) __warn_deprecated; +uint32_t arm_gic_acknowledge_interrupt(void) __warn_deprecated; +void arm_gic_end_of_interrupt(uint32_t id) __warn_deprecated; +uint32_t arm_gic_get_interrupt_type(uint32_t id) __warn_deprecated; #endif /* __GIC_H__ */ diff --git a/include/drivers/arm/gic_common.h b/include/drivers/arm/gic_common.h new file mode 100644 index 00000000..6a322a22 --- /dev/null +++ b/include/drivers/arm/gic_common.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __GIC_COMMON_H__ +#define __GIC_COMMON_H__ + +/******************************************************************************* + * GIC Distributor interface general definitions + ******************************************************************************/ +/* Constants to categorise interrupts */ +#define MIN_SGI_ID 0 +#define MIN_PPI_ID 16 +#define MIN_SPI_ID 32 + +/* Mask for the priority field common to all GIC interfaces */ +#define GIC_PRI_MASK 0xff + +/* Constant to indicate a spurious interrupt in all GIC versions */ +#define GIC_SPURIOUS_INTERRUPT 1023 + +/* Constants to categorise priorities */ +#define GIC_HIGHEST_SEC_PRIORITY 0 +#define GIC_LOWEST_SEC_PRIORITY 127 +#define GIC_HIGHEST_NS_PRIORITY 128 +#define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */ + +/******************************************************************************* + * GIC Distributor interface register offsets that are common to GICv3 & GICv2 + ******************************************************************************/ +#define GICD_CTLR 0x0 +#define GICD_TYPER 0x4 +#define GICD_IIDR 0x8 +#define GICD_IGROUPR 0x80 +#define GICD_ISENABLER 0x100 +#define GICD_ICENABLER 0x180 +#define GICD_ISPENDR 0x200 +#define GICD_ICPENDR 0x280 +#define GICD_ISACTIVER 0x300 +#define GICD_ICACTIVER 0x380 +#define GICD_IPRIORITYR 0x400 +#define GICD_ICFGR 0xc00 +#define GICD_NSACR 0xe00 + +/* GICD_CTLR bit definitions */ +#define CTLR_ENABLE_G0_SHIFT 0 +#define CTLR_ENABLE_G0_MASK 0x1 +#define CTLR_ENABLE_G0_BIT (1 << CTLR_ENABLE_G0_SHIFT) + + +/******************************************************************************* + * GIC Distributor interface register constants that are common to GICv3 & GICv2 + ******************************************************************************/ +#define PIDR2_ARCH_REV_SHIFT 4 +#define PIDR2_ARCH_REV_MASK 0xf + +/* GICv3 revision as reported by the PIDR2 register */ +#define ARCH_REV_GICV3 0x3 +/* GICv2 revision as reported by the PIDR2 register */ +#define ARCH_REV_GICV2 0x2 + +#define IGROUPR_SHIFT 5 +#define ISENABLER_SHIFT 5 +#define ICENABLER_SHIFT ISENABLER_SHIFT +#define ISPENDR_SHIFT 5 +#define ICPENDR_SHIFT ISPENDR_SHIFT +#define ISACTIVER_SHIFT 5 +#define ICACTIVER_SHIFT ISACTIVER_SHIFT +#define IPRIORITYR_SHIFT 2 +#define ICFGR_SHIFT 4 +#define NSACR_SHIFT 4 + +/* GICD_TYPER shifts and masks */ +#define TYPER_IT_LINES_NO_SHIFT 0 +#define TYPER_IT_LINES_NO_MASK 0x1f + +/* Value used to initialize Normal world interrupt priorities four at a time */ +#define GICD_IPRIORITYR_DEF_VAL \ + (GIC_HIGHEST_NS_PRIORITY | \ + (GIC_HIGHEST_NS_PRIORITY << 8) | \ + (GIC_HIGHEST_NS_PRIORITY << 16) | \ + (GIC_HIGHEST_NS_PRIORITY << 24)) + +#ifndef __ASSEMBLY__ + +#include <mmio.h> +#include <stdint.h> + +/******************************************************************************* + * GIC Distributor interface register accessors that are common to GICv3 & GICv2 + ******************************************************************************/ +static inline unsigned int gicd_read_ctlr(uintptr_t base) +{ + return mmio_read_32(base + GICD_CTLR); +} + +static inline unsigned int gicd_read_typer(uintptr_t base) +{ + return mmio_read_32(base + GICD_TYPER); +} + +static inline unsigned int gicd_read_iidr(uintptr_t base) +{ + return mmio_read_32(base + GICD_IIDR); +} + +static inline void gicd_write_ctlr(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICD_CTLR, val); +} + +/******************************************************************************* + * GIC Distributor function prototypes + ******************************************************************************/ +unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id); +unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id); +unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id); +unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id); +unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id); +unsigned int gicd_read_isactiver(uintptr_t base, unsigned int id); +unsigned int gicd_read_icactiver(uintptr_t base, unsigned int id); +unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int id); +unsigned int gicd_read_icfgr(uintptr_t base, unsigned int id); +unsigned int gicd_read_nsacr(uintptr_t base, unsigned int id); +void gicd_write_igroupr(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_isenabler(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_icenabler(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_ispendr(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_icpendr(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_isactiver(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_icactiver(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_icfgr(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_nsacr(uintptr_t base, unsigned int id, unsigned int val); +unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id); +void gicd_set_igroupr(uintptr_t base, unsigned int id); +void gicd_clr_igroupr(uintptr_t base, unsigned int id); +void gicd_set_isenabler(uintptr_t base, unsigned int id); +void gicd_set_icenabler(uintptr_t base, unsigned int id); +void gicd_set_ispendr(uintptr_t base, unsigned int id); +void gicd_set_icpendr(uintptr_t base, unsigned int id); +void gicd_set_isactiver(uintptr_t base, unsigned int id); +void gicd_set_icactiver(uintptr_t base, unsigned int id); + + +#endif /* __ASSEMBLY__ */ +#endif /* __GIC_COMMON_H__ */ diff --git a/include/drivers/arm/gic_v2.h b/include/drivers/arm/gic_v2.h index ce9311e8..594ce499 100644 --- a/include/drivers/arm/gic_v2.h +++ b/include/drivers/arm/gic_v2.h @@ -31,6 +31,13 @@ #ifndef __GIC_V2_H__ #define __GIC_V2_H__ +/****************************************************************************** + * THIS DRIVER IS DEPRECATED. For GICv2 systems, use the driver in gicv2.h + * and for GICv3 systems, use the driver in gicv3.h. + *****************************************************************************/ +#if ERROR_DEPRECATED +#error " The legacy ARM GIC driver is deprecated." +#endif #define GIC400_NUM_SPIS 480 #define MAX_PPIS 14 diff --git a/include/drivers/arm/gic_v3.h b/include/drivers/arm/gic_v3.h index c4106266..a1b6f1b3 100644 --- a/include/drivers/arm/gic_v3.h +++ b/include/drivers/arm/gic_v3.h @@ -31,6 +31,14 @@ #ifndef __GIC_V3_H__ #define __GIC_V3_H__ +/****************************************************************************** + * THIS DRIVER IS DEPRECATED. For GICv2 systems, use the driver in gicv2.h + * and for GICv3 systems, use the driver in gicv3.h. + *****************************************************************************/ +#if ERROR_DEPRECATED +#error " The legacy ARM GIC driver is deprecated." +#endif + #include <mmio.h> #include <stdint.h> diff --git a/include/drivers/arm/gicv2.h b/include/drivers/arm/gicv2.h new file mode 100644 index 00000000..88dc0153 --- /dev/null +++ b/include/drivers/arm/gicv2.h @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __GICV2_H__ +#define __GICV2_H__ + +/******************************************************************************* + * GICv2 miscellaneous definitions + ******************************************************************************/ +/* Interrupt IDs reported by the HPPIR and IAR registers */ +#define PENDING_G1_INTID 1022 + +/******************************************************************************* + * GICv2 specific Distributor interface register offsets and constants. + ******************************************************************************/ +#define GICD_ITARGETSR 0x800 +#define GICD_SGIR 0xF00 +#define GICD_CPENDSGIR 0xF10 +#define GICD_SPENDSGIR 0xF20 +#define GICD_PIDR2_GICV2 0xFE8 + +#define ITARGETSR_SHIFT 2 +#define GIC_TARGET_CPU_MASK 0xff + +#define CPENDSGIR_SHIFT 2 +#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT + +/******************************************************************************* + * GICv2 specific CPU interface register offsets and constants. + ******************************************************************************/ +/* Physical CPU Interface registers */ +#define GICC_CTLR 0x0 +#define GICC_PMR 0x4 +#define GICC_BPR 0x8 +#define GICC_IAR 0xC +#define GICC_EOIR 0x10 +#define GICC_RPR 0x14 +#define GICC_HPPIR 0x18 +#define GICC_AHPPIR 0x28 +#define GICC_IIDR 0xFC +#define GICC_DIR 0x1000 +#define GICC_PRIODROP GICC_EOIR + +/* GICC_CTLR bit definitions */ +#define EOI_MODE_NS (1 << 10) +#define EOI_MODE_S (1 << 9) +#define IRQ_BYP_DIS_GRP1 (1 << 8) +#define FIQ_BYP_DIS_GRP1 (1 << 7) +#define IRQ_BYP_DIS_GRP0 (1 << 6) +#define FIQ_BYP_DIS_GRP0 (1 << 5) +#define CBPR (1 << 4) +#define FIQ_EN_SHIFT 3 +#define FIQ_EN_BIT (1 << FIQ_EN_SHIFT) +#define ACK_CTL (1 << 2) + +/* GICC_IIDR bit masks and shifts */ +#define GICC_IIDR_PID_SHIFT 20 +#define GICC_IIDR_ARCH_SHIFT 16 +#define GICC_IIDR_REV_SHIFT 12 +#define GICC_IIDR_IMP_SHIFT 0 + +#define GICC_IIDR_PID_MASK 0xfff +#define GICC_IIDR_ARCH_MASK 0xf +#define GICC_IIDR_REV_MASK 0xf +#define GICC_IIDR_IMP_MASK 0xfff + +/* HYP view virtual CPU Interface registers */ +#define GICH_CTL 0x0 +#define GICH_VTR 0x4 +#define GICH_ELRSR0 0x30 +#define GICH_ELRSR1 0x34 +#define GICH_APR0 0xF0 +#define GICH_LR_BASE 0x100 + +/* Virtual CPU Interface registers */ +#define GICV_CTL 0x0 +#define GICV_PRIMASK 0x4 +#define GICV_BP 0x8 +#define GICV_INTACK 0xC +#define GICV_EOI 0x10 +#define GICV_RUNNINGPRI 0x14 +#define GICV_HIGHESTPEND 0x18 +#define GICV_DEACTIVATE 0x1000 + +/* GICD_CTLR bit definitions */ +#define CTLR_ENABLE_G1_SHIFT 1 +#define CTLR_ENABLE_G1_MASK 0x1 +#define CTLR_ENABLE_G1_BIT (1 << CTLR_ENABLE_G1_SHIFT) + +/* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */ +#define INT_ID_MASK 0x3ff + +#ifndef __ASSEMBLY__ + +#include <stdint.h> + +/******************************************************************************* + * This structure describes some of the implementation defined attributes of + * the GICv2 IP. It is used by the platform port to specify these attributes + * in order to initialize the GICv2 driver. The attributes are described + * below. + * + * 1. The 'gicd_base' field contains the base address of the Distributor + * interface programmer's view. + * + * 2. The 'gicc_base' field contains the base address of the CPU Interface + * programmer's view. + * + * 3. The 'g0_interrupt_array' field is a pointer to an array in which each + * entry corresponds to an ID of a Group 0 interrupt. + * + * 4. The 'g0_interrupt_num' field contains the number of entries in the + * 'g0_interrupt_array'. + ******************************************************************************/ +typedef struct gicv2_driver_data { + uintptr_t gicd_base; + uintptr_t gicc_base; + unsigned int g0_interrupt_num; + const unsigned int *g0_interrupt_array; +} gicv2_driver_data_t; + +/******************************************************************************* + * Function prototypes + ******************************************************************************/ +void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data); +void gicv2_distif_init(void); +void gicv2_pcpu_distif_init(void); +void gicv2_cpuif_enable(void); +void gicv2_cpuif_disable(void); +unsigned int gicv2_is_fiq_enabled(void); +unsigned int gicv2_get_pending_interrupt_type(void); +unsigned int gicv2_get_pending_interrupt_id(void); +unsigned int gicv2_acknowledge_interrupt(void); +void gicv2_end_of_interrupt(unsigned int id); +unsigned int gicv2_get_interrupt_group(unsigned int id); + +#endif /* __ASSEMBLY__ */ +#endif /* __GICV2_H__ */ diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h new file mode 100644 index 00000000..e874f5cd --- /dev/null +++ b/include/drivers/arm/gicv3.h @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __GICV3_H__ +#define __GICV3_H__ + +/******************************************************************************* + * GICv3 miscellaneous definitions + ******************************************************************************/ +/* Interrupt group definitions */ +#define INT_TYPE_G1S 0 +#define INT_TYPE_G0 1 +#define INT_TYPE_G1NS 2 + +/* Interrupt IDs reported by the HPPIR and IAR registers */ +#define PENDING_G1S_INTID 1020 +#define PENDING_G1NS_INTID 1021 + +/* Constant to categorize LPI interrupt */ +#define MIN_LPI_ID 8192 + +/******************************************************************************* + * GICv3 specific Distributor interface register offsets and constants. + ******************************************************************************/ +#define GICD_STATUSR 0x10 +#define GICD_SETSPI_NSR 0x40 +#define GICD_CLRSPI_NSR 0x48 +#define GICD_SETSPI_SR 0x50 +#define GICD_CLRSPI_SR 0x50 +#define GICD_IGRPMODR 0xd00 +#define GICD_IROUTER 0x6100 +#define GICD_PIDR2_GICV3 0xffe8 + +#define IGRPMODR_SHIFT 5 + +/* GICD_CTLR bit definitions */ +#define CTLR_ENABLE_G1NS_SHIFT 1 +#define CTLR_ENABLE_G1S_SHIFT 2 +#define CTLR_ARE_S_SHIFT 4 +#define CTLR_ARE_NS_SHIFT 5 +#define CTLR_DS_SHIFT 6 +#define CTLR_E1NWF_SHIFT 7 +#define GICD_CTLR_RWP_SHIFT 31 + +#define CTLR_ENABLE_G1NS_MASK 0x1 +#define CTLR_ENABLE_G1S_MASK 0x1 +#define CTLR_ARE_S_MASK 0x1 +#define CTLR_ARE_NS_MASK 0x1 +#define CTLR_DS_MASK 0x1 +#define CTLR_E1NWF_MASK 0x1 +#define GICD_CTLR_RWP_MASK 0x1 + +#define CTLR_ENABLE_G1NS_BIT (1 << CTLR_ENABLE_G1NS_SHIFT) +#define CTLR_ENABLE_G1S_BIT (1 << CTLR_ENABLE_G1S_SHIFT) +#define CTLR_ARE_S_BIT (1 << CTLR_ARE_S_SHIFT) +#define CTLR_ARE_NS_BIT (1 << CTLR_ARE_NS_SHIFT) +#define CTLR_DS_BIT (1 << CTLR_DS_SHIFT) +#define CTLR_E1NWF_BIT (1 << CTLR_E1NWF_SHIFT) +#define GICD_CTLR_RWP_BIT (1 << GICD_CTLR_RWP_SHIFT) + +/* GICD_IROUTER shifts and masks */ +#define IROUTER_IRM_SHIFT 31 +#define IROUTER_IRM_MASK 0x1 + +/******************************************************************************* + * GICv3 Re-distributor interface registers & constants + ******************************************************************************/ +#define GICR_PCPUBASE_SHIFT 0x11 +#define GICR_SGIBASE_OFFSET (1 << 0x10) /* 64 KB */ +#define GICR_CTLR 0x0 +#define GICR_TYPER 0x08 +#define GICR_WAKER 0x14 +#define GICR_IGROUPR0 (GICR_SGIBASE_OFFSET + 0x80) +#define GICR_ISENABLER0 (GICR_SGIBASE_OFFSET + 0x100) +#define GICR_ICENABLER0 (GICR_SGIBASE_OFFSET + 0x180) +#define GICR_IPRIORITYR (GICR_SGIBASE_OFFSET + 0x400) +#define GICR_ICFGR0 (GICR_SGIBASE_OFFSET + 0xc00) +#define GICR_ICFGR1 (GICR_SGIBASE_OFFSET + 0xc04) +#define GICR_IGRPMODR0 (GICR_SGIBASE_OFFSET + 0xd00) + +/* GICR_CTLR bit definitions */ +#define GICR_CTLR_RWP_SHIFT 3 +#define GICR_CTLR_RWP_MASK 0x1 +#define GICR_CTLR_RWP_BIT (1 << GICR_CTLR_RWP_SHIFT) + +/* GICR_WAKER bit definitions */ +#define WAKER_CA_SHIFT 2 +#define WAKER_PS_SHIFT 1 + +#define WAKER_CA_MASK 0x1 +#define WAKER_PS_MASK 0x1 + +#define WAKER_CA_BIT (1 << WAKER_CA_SHIFT) +#define WAKER_PS_BIT (1 << WAKER_PS_SHIFT) + +/* GICR_TYPER bit definitions */ +#define TYPER_AFF_VAL_SHIFT 32 +#define TYPER_PROC_NUM_SHIFT 8 +#define TYPER_LAST_SHIFT 4 + +#define TYPER_AFF_VAL_MASK 0xffffffff +#define TYPER_PROC_NUM_MASK 0xffff +#define TYPER_LAST_MASK 0x1 + +#define TYPER_LAST_BIT (1 << TYPER_LAST_SHIFT) + +/******************************************************************************* + * GICv3 CPU interface registers & constants + ******************************************************************************/ +/* ICC_SRE bit definitions*/ +#define ICC_SRE_EN_BIT (1 << 3) +#define ICC_SRE_DIB_BIT (1 << 2) +#define ICC_SRE_DFB_BIT (1 << 1) +#define ICC_SRE_SRE_BIT (1 << 0) + +/* ICC_IGRPEN1_EL3 bit definitions */ +#define IGRPEN1_EL3_ENABLE_G1NS_SHIFT 0 +#define IGRPEN1_EL3_ENABLE_G1S_SHIFT 1 + +#define IGRPEN1_EL3_ENABLE_G1NS_BIT (1 << IGRPEN1_EL3_ENABLE_G1NS_SHIFT) +#define IGRPEN1_EL3_ENABLE_G1S_BIT (1 << IGRPEN1_EL3_ENABLE_G1S_SHIFT) + +/* ICC_IGRPEN0_EL1 bit definitions */ +#define IGRPEN1_EL1_ENABLE_G0_SHIFT 0 +#define IGRPEN1_EL1_ENABLE_G0_BIT (1 << IGRPEN1_EL1_ENABLE_G0_SHIFT) + +/* ICC_HPPIR0_EL1 bit definitions */ +#define HPPIR0_EL1_INTID_SHIFT 0 +#define HPPIR0_EL1_INTID_MASK 0xffffff + +/* ICC_HPPIR1_EL1 bit definitions */ +#define HPPIR1_EL1_INTID_SHIFT 0 +#define HPPIR1_EL1_INTID_MASK 0xffffff + +/* ICC_IAR0_EL1 bit definitions */ +#define IAR0_EL1_INTID_SHIFT 0 +#define IAR0_EL1_INTID_MASK 0xffffff + +/* ICC_IAR1_EL1 bit definitions */ +#define IAR1_EL1_INTID_SHIFT 0 +#define IAR1_EL1_INTID_MASK 0xffffff + +#ifndef __ASSEMBLY__ + +#include <stdint.h> + +#define gicv3_is_intr_id_special_identifier(id) \ + (((id) >= PENDING_G1S_INTID) && ((id) <= GIC_SPURIOUS_INTERRUPT)) + +/******************************************************************************* + * Helper GICv3 macros for SEL1 + ******************************************************************************/ +#define gicv3_acknowledge_interrupt_sel1() read_icc_iar1_el1() &\ + IAR1_EL1_INTID_MASK +#define gicv3_get_pending_interrupt_id_sel1() read_icc_hppir1_el1() &\ + HPPIR1_EL1_INTID_MASK +#define gicv3_end_of_interrupt_sel1(id) write_icc_eoir1_el1(id) + + +/******************************************************************************* + * Helper GICv3 macros for EL3 + ******************************************************************************/ +#define gicv3_acknowledge_interrupt() read_icc_iar0_el1() &\ + IAR0_EL1_INTID_MASK +#define gicv3_end_of_interrupt(id) write_icc_eoir0_el1(id) + +/******************************************************************************* + * This structure describes some of the implementation defined attributes of the + * GICv3 IP. It is used by the platform port to specify these attributes in order + * to initialise the GICV3 driver. The attributes are described below. + * + * 1. The 'gicd_base' field contains the base address of the Distributor + * interface programmer's view. + * + * 2. The 'gicr_base' field contains the base address of the Re-distributor + * interface programmer's view. + * + * 3. The 'g0_interrupt_array' field is a ponter to an array in which each + * entry corresponds to an ID of a Group 0 interrupt. + * + * 4. The 'g0_interrupt_num' field contains the number of entries in the + * 'g0_interrupt_array'. + * + * 5. The 'g1s_interrupt_array' field is a ponter to an array in which each + * entry corresponds to an ID of a Group 1 interrupt. + * + * 6. The 'g1s_interrupt_num' field contains the number of entries in the + * 'g1s_interrupt_array'. + * + * 7. The 'rdistif_num' field contains the number of Redistributor interfaces + * the GIC implements. This is equal to the number of CPUs or CPU interfaces + * instantiated in the GIC. + * + * 8. The 'rdistif_base_addrs' field is a pointer to an array that has an entry + * for storing the base address of the Redistributor interface frame of each + * CPU in the system. The size of the array = 'rdistif_num'. The base + * addresses are detected during driver initialisation. + * + * 9. The 'mpidr_to_core_pos' field is a pointer to a hash function which the + * driver will use to convert an MPIDR value to a linear core index. This + * index will be used for accessing the 'rdistif_base_addrs' array. This is + * an optional field. A GICv3 implementation maps each MPIDR to a linear core + * index as well. This mapping can be found by reading the "Affinity Value" + * and "Processor Number" fields in the GICR_TYPER. It is IMP. DEF. if the + * "Processor Numbers" are suitable to index into an array to access core + * specific information. If this not the case, the platform port must provide + * a hash function. Otherwise, the "Processor Number" field will be used to + * access the array elements. + ******************************************************************************/ +typedef unsigned int (*mpidr_hash_fn)(unsigned long mpidr); + +typedef struct gicv3_driver_data { + uintptr_t gicd_base; + uintptr_t gicr_base; + unsigned int g0_interrupt_num; + unsigned int g1s_interrupt_num; + const unsigned int *g0_interrupt_array; + const unsigned int *g1s_interrupt_array; + unsigned int rdistif_num; + uintptr_t *rdistif_base_addrs; + mpidr_hash_fn mpidr_to_core_pos; +} gicv3_driver_data_t; + +/******************************************************************************* + * GICv3 EL3 driver API + ******************************************************************************/ +void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data); +void gicv3_distif_init(void); +void gicv3_rdistif_init(unsigned int proc_num); +void gicv3_cpuif_enable(unsigned int proc_num); +void gicv3_cpuif_disable(unsigned int proc_num); +unsigned int gicv3_get_pending_interrupt_type(void); +unsigned int gicv3_get_pending_interrupt_id(void); +unsigned int gicv3_get_interrupt_type(unsigned int id, + unsigned int proc_num); + + +#endif /* __ASSEMBLY__ */ +#endif /* __GICV3_H__ */ diff --git a/include/drivers/arm/sp805.h b/include/drivers/arm/sp805.h new file mode 100644 index 00000000..6bd81587 --- /dev/null +++ b/include/drivers/arm/sp805.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SP805_H__ +#define __SP805_H__ + +/* SP805 register offset */ +#define SP805_WDOG_LOAD_OFF 0x000 +#define SP805_WDOG_CTR_OFF 0x008 +#define SP805_WDOG_LOCK_OFF 0xc00 + +/* Magic word to unlock the wd registers */ +#define WDOG_UNLOCK_KEY 0x1ACCE551 + +/* Register field definitions */ +#define SP805_CTR_RESEN (1 << 1) +#define SP805_CTR_INTEN (1 << 0) + +#ifndef __ASSEMBLY__ + +#include <stdint.h> + +/* Public high level API */ + +void sp805_start(uintptr_t base, unsigned long ticks); +void sp805_stop(uintptr_t base); +void sp805_refresh(uintptr_t base, unsigned long ticks); + +#endif /* __ASSEMBLY__ */ + +#endif /* __SP805_H__ */ diff --git a/include/drivers/arm/tzc400.h b/include/drivers/arm/tzc400.h index a5312c47..f8e1664e 100644 --- a/include/drivers/arm/tzc400.h +++ b/include/drivers/arm/tzc400.h @@ -147,7 +147,9 @@ #define TZC_REGION_ACCESS_RDWR(id) \ (TZC_REGION_ACCESS_RD(id) | TZC_REGION_ACCESS_WR(id)) -#define TZC400_COMPONENT_ID 0xb105f00d +/* Consist of part_number_1 and part_number_0 */ +#define TZC400_PERIPHERAL_ID 0x0460 + #ifndef __ASSEMBLY__ diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 9aea2c9d..49efafc5 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -88,6 +88,14 @@ #define ICC_CTLR_EL1 S3_0_C12_C12_4 #define ICC_CTLR_EL3 S3_6_C12_C12_4 #define ICC_PMR_EL1 S3_0_C4_C6_0 +#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 +#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 +#define ICC_HPPIR0_EL1 S3_0_c12_c8_2 +#define ICC_HPPIR1_EL1 S3_0_c12_c12_2 +#define ICC_IAR0_EL1 S3_0_c12_c8_0 +#define ICC_IAR1_EL1 S3_0_c12_c12_0 +#define ICC_EOIR0_EL1 S3_0_c12_c8_1 +#define ICC_EOIR1_EL1 S3_0_c12_c12_1 /******************************************************************************* * Generic timer memory mapped registers & offsets @@ -122,6 +130,10 @@ #define ID_AA64PFR0_EL3_SHIFT 12 #define ID_AA64PFR0_ELX_MASK 0xf +#define ID_AA64PFR0_GIC_SHIFT 24 +#define ID_AA64PFR0_GIC_WIDTH 4 +#define ID_AA64PFR0_GIC_MASK ((1 << ID_AA64PFR0_GIC_WIDTH) - 1) + /* ID_PFR1_EL1 definitions */ #define ID_PFR1_VIRTEXT_SHIFT 12 #define ID_PFR1_VIRTEXT_MASK 0xf diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h index d01ea315..43c6917e 100644 --- a/include/lib/aarch64/arch_helpers.h +++ b/include/lib/aarch64/arch_helpers.h @@ -74,6 +74,14 @@ static inline void write_ ## _name(const uint64_t v) \ _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) +/* Define read function for renamed system register */ +#define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \ + _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) + +/* Define write function for renamed system register */ +#define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \ + _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) + /* Define write function for special system registers */ #define DEFINE_SYSREG_WRITE_CONST_FUNC(_name) \ _DEFINE_SYSREG_WRITE_CONST_FUNC(_name, _name) @@ -284,12 +292,18 @@ DEFINE_SYSREG_READ_FUNC(isr_el1) DEFINE_SYSREG_READ_FUNC(ctr_el0) -/* GICv3 System Registers */ - DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2) DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3) DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1) +DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3) +DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1) +DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1) +DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1) +DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1) +DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1) +DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1) +DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1) #define IS_IN_EL(x) \ diff --git a/include/plat/arm/board/common/board_arm_oid.h b/include/plat/arm/board/common/board_arm_oid.h index 92a9bd1e..b29212e4 100644 --- a/include/plat/arm/board/common/board_arm_oid.h +++ b/include/plat/arm/board/common/board_arm_oid.h @@ -32,39 +32,136 @@ #define __BOARD_ARM_OID_H__ /* - * This is the list of the different extensions containing relevant information - * to establish the chain of trust. + * The following is a list of OID values defined and reserved by ARM, which + * are used to define the extension fields of the certificate structure, as + * defined in the Trusted Board Boot Requirements (TBBR) specification, + * ARM DEN0006C-1. * - * The OIDs shown here are just an example. Real OIDs should be obtained from - * the ITU-T. + * Non-ARM platform owners that wish to align with the TBBR should define + * constants with the same name in their own platform port(s), using their + * own OIDs obtained from the ITU-T. */ -/* Non-volatile counter extensions */ -#define TZ_FW_NVCOUNTER_OID "1.2.3.1" -#define NTZ_FW_NVCOUNTER_OID "1.2.3.2" -/* BL2 extensions */ -#define BL2_HASH_OID "1.2.3.3" +/* TrustedFirmwareNVCounter - Non-volatile counter extension */ +#define TZ_FW_NVCOUNTER_OID "1.3.6.1.4.1.4128.2100.1" +/* NonTrustedFirmwareNVCounter - Non-volatile counter extension */ +#define NTZ_FW_NVCOUNTER_OID "1.3.6.1.4.1.4128.2100.2" -/* Trusted Key extensions */ -#define TZ_WORLD_PK_OID "1.2.3.4" -#define NTZ_WORLD_PK_OID "1.2.3.5" -/* BL3-1 extensions */ -#define BL31_CONTENT_CERT_PK_OID "1.2.3.6" -#define BL31_HASH_OID "1.2.3.7" +/* + * Non-Trusted Firmware Updater Certificate + */ + +/* APFirmwareUpdaterConfigHash - BL2U */ +#define BL2U_HASH_OID "1.3.6.1.4.1.4128.2100.101" +/* SCPFirmwareUpdaterConfigHash - SCP_BL2U */ +#define SCP_BL2U_HASH_OID "1.3.6.1.4.1.4128.2100.102" +/* FirmwareUpdaterHash - NS_BL2U */ +#define NS_BL2U_HASH_OID "1.3.6.1.4.1.4128.2100.103" +/* TrustedWatchdogRefreshTime */ +#define TRUSTED_WATCHDOG_TIME_OID "1.3.6.1.4.1.4128.2100.104" + + +/* + * Trusted Boot Firmware Certificate + */ + +/* TrustedBootFirmwareHash - BL2 */ +#define BL2_HASH_OID "1.3.6.1.4.1.4128.2100.201" + + +/* + * Trusted Key Certificate + */ + +/* PrimaryDebugCertificatePK */ +#define PRIMARY_DEBUG_PK_OID "1.3.6.1.4.1.4128.2100.301" +/* TrustedWorldPK */ +#define TZ_WORLD_PK_OID "1.3.6.1.4.1.4128.2100.302" +/* NonTrustedWorldPK */ +#define NTZ_WORLD_PK_OID "1.3.6.1.4.1.4128.2100.303" + + +/* + * Trusted Debug Certificate + */ + +/* DebugScenario */ +#define TRUSTED_DEBUG_SCENARIO_OID "1.3.6.1.4.1.4128.2100.401" +/* SoC Specific */ +#define TRUSTED_DEBUG_SOC_SPEC_OID "1.3.6.1.4.1.4128.2100.402" +/* SecondaryDebugCertPK */ +#define SECONDARY_DEBUG_PK_OID "1.3.6.1.4.1.4128.2100.403" + + +/* + * SoC Firmware Key Certificate + */ + +/* SoCFirmwareContentCertPK */ +#define BL31_CONTENT_CERT_PK_OID "1.3.6.1.4.1.4128.2100.501" + + +/* + * SoC Firmware Content Certificate + */ -/* BL3-0 extensions */ -#define BL30_CONTENT_CERT_PK_OID "1.2.3.8" -#define BL30_HASH_OID "1.2.3.9" +/* APRomPatchHash - BL1_PATCH */ +#define APROM_PATCH_HASH_OID "1.3.6.1.4.1.4128.2100.601" +/* SoCConfigHash */ +#define SOC_CONFIG_HASH_OID "1.3.6.1.4.1.4128.2100.602" +/* SoCAPFirmwareHash - BL31 */ +#define BL31_HASH_OID "1.3.6.1.4.1.4128.2100.603" -/* BL3-2 extensions */ -#define BL32_CONTENT_CERT_PK_OID "1.2.3.10" -#define BL32_HASH_OID "1.2.3.11" -/* BL3-3 extensions */ -#define BL33_CONTENT_CERT_PK_OID "1.2.3.12" -#define BL33_HASH_OID "1.2.3.13" +/* + * SCP Firmware Key Certificate + */ + +/* SCPFirmwareContentCertPK */ +#define BL30_CONTENT_CERT_PK_OID "1.3.6.1.4.1.4128.2100.701" + + +/* + * SCP Firmware Content Certificate + */ + +/* SCPFirmwareHash - BL30 */ +#define BL30_HASH_OID "1.3.6.1.4.1.4128.2100.801" +/* SCPRomPatchHash - BL0_PATCH */ +#define SCP_ROM_PATCH_HASH_OID "1.3.6.1.4.1.4128.2100.802" + + +/* + * Trusted OS Firmware Key Certificate + */ + +/* TrustedOSFirmwareContentCertPK */ +#define BL32_CONTENT_CERT_PK_OID "1.3.6.1.4.1.4128.2100.901" + + +/* + * Trusted OS Firmware Content Certificate + */ + +/* TrustedOSFirmwareHash - BL32 */ +#define BL32_HASH_OID "1.3.6.1.4.1.4128.2100.1001" + + +/* + * Non-Trusted Firmware Key Certificate + */ + +/* NonTrustedFirmwareContentCertPK */ +#define BL33_CONTENT_CERT_PK_OID "1.3.6.1.4.1.4128.2100.1101" + + +/* + * Non-Trusted Firmware Content Certificate + */ +/* NonTrustedWorldBootloaderHash - BL33 */ +#define BL33_HASH_OID "1.3.6.1.4.1.4128.2100.1201" #endif /* __BOARD_ARM_OID_H__ */ diff --git a/include/plat/arm/board/common/drivers/norflash.h b/include/plat/arm/board/common/drivers/norflash.h new file mode 100644 index 00000000..0bf35a50 --- /dev/null +++ b/include/plat/arm/board/common/drivers/norflash.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __NORFLASH_H_ +#define __NORFLASH_H_ + +#include <stdint.h> + +/* First bus cycle */ +#define NOR_CMD_READ_ARRAY 0xFF +#define NOR_CMD_READ_ID_CODE 0x90 +#define NOR_CMD_READ_QUERY 0x98 +#define NOR_CMD_READ_STATUS_REG 0x70 +#define NOR_CMD_CLEAR_STATUS_REG 0x50 +#define NOR_CMD_WRITE_TO_BUFFER 0xE8 +#define NOR_CMD_WORD_PROGRAM 0x40 +#define NOR_CMD_BLOCK_ERASE 0x20 +#define NOR_CMD_LOCK_UNLOCK 0x60 + +/* Second bus cycle */ +#define NOR_LOCK_BLOCK 0x01 +#define NOR_UNLOCK_BLOCK 0xD0 + +/* Status register bits */ +#define NOR_DWS (1 << 7) +#define NOR_ESS (1 << 6) +#define NOR_ES (1 << 5) +#define NOR_PS (1 << 4) +#define NOR_VPPS (1 << 3) +#define NOR_PSS (1 << 2) +#define NOR_BLS (1 << 1) +#define NOR_BWS (1 << 0) + +/* Public API */ +void nor_send_cmd(uintptr_t base_addr, unsigned long cmd); +int nor_word_program(uintptr_t base_addr, unsigned long data); +void nor_lock(uintptr_t base_addr); +void nor_unlock(uintptr_t base_addr); + +#endif /* __NORFLASH_H_ */ + diff --git a/include/plat/arm/board/common/v2m_def.h b/include/plat/arm/board/common/v2m_def.h index 7a4ef5ad..7ed0af6c 100644 --- a/include/plat/arm/board/common/v2m_def.h +++ b/include/plat/arm/board/common/v2m_def.h @@ -38,6 +38,9 @@ #define V2M_SYS_ID 0x0 #define V2M_SYS_SWITCH 0x4 #define V2M_SYS_LED 0x8 +#define V2M_SYS_NVFLAGS 0x38 +#define V2M_SYS_NVFLAGSSET 0x38 +#define V2M_SYS_NVFLAGSCLR 0x3c #define V2M_SYS_CFGDATA 0xa0 #define V2M_SYS_CFGCTRL 0xa4 #define V2M_SYS_CFGSTATUS 0xa8 @@ -109,7 +112,11 @@ #define V2M_SP804_TIMER0_BASE 0x1C110000 #define V2M_SP804_TIMER1_BASE 0x1C120000 -#define V2M_MAP_FLASH0 MAP_REGION_FLAT(V2M_FLASH0_BASE,\ +#define V2M_MAP_FLASH0_RW MAP_REGION_FLAT(V2M_FLASH0_BASE,\ + V2M_FLASH0_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define V2M_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ V2M_FLASH0_SIZE, \ MT_MEMORY | MT_RO | MT_SECURE) diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index 452c3856..4726d5e5 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -175,6 +175,15 @@ #define ARM_CONSOLE_BAUDRATE 115200 +/* Trusted Watchdog constants */ +#define ARM_SP805_TWDG_BASE 0x2a490000 +#define ARM_SP805_TWDG_CLK_HZ 32768 +/* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 + * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ +#define ARM_TWDG_TIMEOUT_SEC 128 +#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ + ARM_TWDG_TIMEOUT_SEC) + /****************************************************************************** * Required platform porting definitions common to all ARM standard platforms *****************************************************************************/ diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index 044e18ef..aadf58d8 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -149,6 +149,7 @@ int arm_validate_power_state(unsigned int power_state, psci_power_state_t *req_state); int arm_validate_ns_entrypoint(uintptr_t entrypoint); void arm_system_pwr_domain_resume(void); +void arm_program_trusted_mailbox(uintptr_t address); /* Topology utility function */ int arm_check_mpidr(u_register_t mpidr); diff --git a/include/plat/common/common_def.h b/include/plat/common/common_def.h index 077080df..43c69cc8 100644 --- a/include/plat/common/common_def.h +++ b/include/plat/common/common_def.h @@ -69,15 +69,10 @@ /* * Macros to wrap declarations of deprecated APIs within Trusted Firmware. - * The callers of these APIs will continue to compile as long as the build - * flag WARN_DEPRECATED is zero. Else the compiler will emit a warning - * when the callers of these APIs are compiled. + * The callers of these APIs will continue to compile with a warning as long + * as the build flag ERROR_DEPRECATED is zero. */ -#if WARN_DEPRECATED #define __warn_deprecated __attribute__ ((deprecated)) -#else -#define __warn_deprecated -#endif #endif /* __COMMON_DEF_H__ */ |