diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/drivers/arm/gic_common.h | 65 | ||||
| -rw-r--r-- | include/drivers/arm/pl011.h | 1 | ||||
| -rw-r--r-- | include/lib/aarch64/arch_helpers.h | 2 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a57.h | 7 | ||||
| -rw-r--r-- | include/plat/arm/board/common/board_arm_def.h | 4 | ||||
| -rw-r--r-- | include/plat/arm/common/aarch64/arm_macros.S | 30 | ||||
| -rw-r--r-- | include/plat/arm/common/aarch64/cci_macros.S | 61 | ||||
| -rw-r--r-- | include/plat/arm/common/arm_config.h | 6 | ||||
| -rw-r--r-- | include/plat/arm/common/arm_def.h | 38 | ||||
| -rw-r--r-- | include/plat/arm/common/plat_arm.h | 16 | ||||
| -rw-r--r-- | include/plat/arm/css/common/css_def.h | 65 |
11 files changed, 128 insertions, 167 deletions
diff --git a/include/drivers/arm/gic_common.h b/include/drivers/arm/gic_common.h index 6a322a22..dd8efdc7 100644 --- a/include/drivers/arm/gic_common.h +++ b/include/drivers/arm/gic_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -107,67 +107,4 @@ (GIC_HIGHEST_NS_PRIORITY << 16) | \ (GIC_HIGHEST_NS_PRIORITY << 24)) -#ifndef __ASSEMBLY__ - -#include <mmio.h> -#include <stdint.h> - -/******************************************************************************* - * GIC Distributor interface register accessors that are common to GICv3 & GICv2 - ******************************************************************************/ -static inline unsigned int gicd_read_ctlr(uintptr_t base) -{ - return mmio_read_32(base + GICD_CTLR); -} - -static inline unsigned int gicd_read_typer(uintptr_t base) -{ - return mmio_read_32(base + GICD_TYPER); -} - -static inline unsigned int gicd_read_iidr(uintptr_t base) -{ - return mmio_read_32(base + GICD_IIDR); -} - -static inline void gicd_write_ctlr(uintptr_t base, unsigned int val) -{ - mmio_write_32(base + GICD_CTLR, val); -} - -/******************************************************************************* - * GIC Distributor function prototypes - ******************************************************************************/ -unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id); -unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id); -unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id); -unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id); -unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id); -unsigned int gicd_read_isactiver(uintptr_t base, unsigned int id); -unsigned int gicd_read_icactiver(uintptr_t base, unsigned int id); -unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int id); -unsigned int gicd_read_icfgr(uintptr_t base, unsigned int id); -unsigned int gicd_read_nsacr(uintptr_t base, unsigned int id); -void gicd_write_igroupr(uintptr_t base, unsigned int id, unsigned int val); -void gicd_write_isenabler(uintptr_t base, unsigned int id, unsigned int val); -void gicd_write_icenabler(uintptr_t base, unsigned int id, unsigned int val); -void gicd_write_ispendr(uintptr_t base, unsigned int id, unsigned int val); -void gicd_write_icpendr(uintptr_t base, unsigned int id, unsigned int val); -void gicd_write_isactiver(uintptr_t base, unsigned int id, unsigned int val); -void gicd_write_icactiver(uintptr_t base, unsigned int id, unsigned int val); -void gicd_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val); -void gicd_write_icfgr(uintptr_t base, unsigned int id, unsigned int val); -void gicd_write_nsacr(uintptr_t base, unsigned int id, unsigned int val); -unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id); -void gicd_set_igroupr(uintptr_t base, unsigned int id); -void gicd_clr_igroupr(uintptr_t base, unsigned int id); -void gicd_set_isenabler(uintptr_t base, unsigned int id); -void gicd_set_icenabler(uintptr_t base, unsigned int id); -void gicd_set_ispendr(uintptr_t base, unsigned int id); -void gicd_set_icpendr(uintptr_t base, unsigned int id); -void gicd_set_isactiver(uintptr_t base, unsigned int id); -void gicd_set_icactiver(uintptr_t base, unsigned int id); - - -#endif /* __ASSEMBLY__ */ #endif /* __GIC_COMMON_H__ */ diff --git a/include/drivers/arm/pl011.h b/include/drivers/arm/pl011.h index d5ea890d..ce6cdcf5 100644 --- a/include/drivers/arm/pl011.h +++ b/include/drivers/arm/pl011.h @@ -71,6 +71,7 @@ #define PL011_UARTFR_TXFF_BIT 5 /* Transmit FIFO full bit in UARTFR register */ #define PL011_UARTFR_RXFE_BIT 4 /* Receive FIFO empty bit in UARTFR register */ +#define PL011_UARTFR_BUSY_BIT 3 /* UART busy bit in UARTFR register */ /* Control reg bits */ #if !PL011_GENERIC_UART diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h index 067b8302..d1ad31dc 100644 --- a/include/lib/aarch64/arch_helpers.h +++ b/include/lib/aarch64/arch_helpers.h @@ -194,6 +194,8 @@ DEFINE_SYSOP_FUNC(wfe) DEFINE_SYSOP_FUNC(sev) DEFINE_SYSOP_TYPE_FUNC(dsb, sy) DEFINE_SYSOP_TYPE_FUNC(dmb, sy) +DEFINE_SYSOP_TYPE_FUNC(dmb, st) +DEFINE_SYSOP_TYPE_FUNC(dmb, ld) DEFINE_SYSOP_TYPE_FUNC(dsb, ish) DEFINE_SYSOP_TYPE_FUNC(dmb, ish) DEFINE_SYSOP_FUNC(isb) diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index c81259c8..c512129a 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -61,8 +61,9 @@ ******************************************************************************/ #define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ -#define CPUACTLR_NO_ALLOC_WBWA (1 << 49) -#define CPUACTLR_DCC_AS_DCCI (1 << 44) +#define CPUACTLR_DIS_OVERREAD (1 << 52) +#define CPUACTLR_NO_ALLOC_WBWA (1 << 49) +#define CPUACTLR_DCC_AS_DCCI (1 << 44) /******************************************************************************* * L2 Control register specific definitions. diff --git a/include/plat/arm/board/common/board_arm_def.h b/include/plat/arm/board/common/board_arm_def.h index b4e43134..db2a8dfb 100644 --- a/include/plat/arm/board/common/board_arm_def.h +++ b/include/plat/arm/board/common/board_arm_def.h @@ -39,9 +39,7 @@ */ /* Size of cacheable stacks */ -#if DEBUG_XLAT_TABLE -# define PLATFORM_STACK_SIZE 0x800 -#elif IMAGE_BL1 +#if IMAGE_BL1 #if TRUSTED_BOARD_BOOT # define PLATFORM_STACK_SIZE 0x1000 #else diff --git a/include/plat/arm/common/aarch64/arm_macros.S b/include/plat/arm/common/aarch64/arm_macros.S index 384bb514..3b19a7d0 100644 --- a/include/plat/arm/common/aarch64/arm_macros.S +++ b/include/plat/arm/common/aarch64/arm_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -30,7 +30,6 @@ #ifndef __ARM_MACROS_S__ #define __ARM_MACROS_S__ -#include <cci.h> #include <gic_common.h> #include <gicv2.h> #include <gicv3.h> @@ -117,31 +116,4 @@ gicd_ispendr_loop: exit_print_gic_regs: .endm - -.section .rodata.cci_reg_name, "aS" -cci_iface_regs: - .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" - - /* ------------------------------------------------ - * The below required platform porting macro prints - * out relevant interconnect registers whenever an - * unhandled exception is taken in BL31. - * Clobbers: x0 - x9, sp - * ------------------------------------------------ - */ - .macro plat_print_interconnect_regs - adr x6, cci_iface_regs - /* Store in x7 the base address of the first interface */ - mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \ - PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX)) - ldr w8, [x7, #SNOOP_CTRL_REG] - /* Store in x7 the base address of the second interface */ - mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \ - PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX)) - ldr w9, [x7, #SNOOP_CTRL_REG] - /* Store to the crash buf and print to console */ - bl str_in_crash_buf_print - .endm - - #endif /* __ARM_MACROS_S__ */ diff --git a/include/plat/arm/common/aarch64/cci_macros.S b/include/plat/arm/common/aarch64/cci_macros.S new file mode 100644 index 00000000..40f9d7e0 --- /dev/null +++ b/include/plat/arm/common/aarch64/cci_macros.S @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __CCI_MACROS_S__ +#define __CCI_MACROS_S__ + +#include <cci.h> +#include <platform_def.h> + +.section .rodata.cci_reg_name, "aS" +cci_iface_regs: + .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" + + /* ------------------------------------------------ + * The below required platform porting macro prints + * out relevant interconnect registers whenever an + * unhandled exception is taken in BL31. + * Clobbers: x0 - x9, sp + * ------------------------------------------------ + */ + .macro plat_print_interconnect_regs + adr x6, cci_iface_regs + /* Store in x7 the base address of the first interface */ + mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \ + PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX)) + ldr w8, [x7, #SNOOP_CTRL_REG] + /* Store in x7 the base address of the second interface */ + mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \ + PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX)) + ldr w9, [x7, #SNOOP_CTRL_REG] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + .endm + +#endif /* __CCI_MACROS_S__ */ diff --git a/include/plat/arm/common/arm_config.h b/include/plat/arm/common/arm_config.h index 24c1f0a1..03808498 100644 --- a/include/plat/arm/common/arm_config.h +++ b/include/plat/arm/common/arm_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -35,8 +35,8 @@ enum arm_config_flags { /* Whether Base memory map is in use */ ARM_CONFIG_BASE_MMAP = 0x1, - /* Whether CCI should be enabled */ - ARM_CONFIG_HAS_CCI = 0x2, + /* Whether interconnect should be enabled */ + ARM_CONFIG_HAS_INTERCONNECT = 0x2, /* Whether TZC should be configured */ ARM_CONFIG_HAS_TZC = 0x4 }; diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index b2db6160..dab75450 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -44,7 +44,6 @@ /* Special value used to verify platform parameters from BL2 to BL31 */ #define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL -#define ARM_CLUSTER_COUNT 2 #define ARM_SYSTEM_COUNT 1 #define ARM_CACHE_WRITEBACK_SHIFT 6 @@ -151,14 +150,10 @@ #define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \ ARM_IRQ_SEC_SGI_6 -#define ARM_SHARED_RAM_ATTR ((PLAT_ARM_SHARED_RAM_CACHED ? \ - MT_MEMORY : MT_DEVICE) \ - | MT_RW | MT_SECURE) - #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ ARM_SHARED_RAM_BASE, \ ARM_SHARED_RAM_SIZE, \ - ARM_SHARED_RAM_ATTR) + MT_DEVICE | MT_RW | MT_SECURE) #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ ARM_NS_DRAM1_BASE, \ @@ -218,10 +213,6 @@ */ #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF - -#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER0_CORE_COUNT + \ - PLAT_ARM_CLUSTER1_CORE_COUNT) - /* * Some data must be aligned on the biggest cache line size in the platform. * This is known only to the platform as it might have a combination of @@ -239,44 +230,31 @@ #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ + PLAT_ARM_TRUSTED_ROM_SIZE) /* - * Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using - * the current BL1 RW debug size plus a little space for growth. + * Put BL1 RW at the top of the Trusted SRAM. */ -#if TRUSTED_BOARD_BOOT #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ ARM_BL_RAM_SIZE - \ - 0x9000) -#else -#define BL1_RW_BASE (ARM_BL_RAM_BASE + \ - ARM_BL_RAM_SIZE - \ - 0x6000) -#endif + PLAT_ARM_MAX_BL1_RW_SIZE) #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) /******************************************************************************* * BL2 specific defines. ******************************************************************************/ /* - * Put BL2 just below BL31. BL2_BASE is calculated using the current BL2 debug - * size plus a little space for growth. + * Put BL2 just below BL31. */ -#if TRUSTED_BOARD_BOOT -#define BL2_BASE (BL31_BASE - 0x1D000) -#else -#define BL2_BASE (BL31_BASE - 0xC000) -#endif +#define BL2_BASE (BL31_BASE - PLAT_ARM_MAX_BL2_SIZE) #define BL2_LIMIT BL31_BASE /******************************************************************************* * BL31 specific defines. ******************************************************************************/ /* - * Put BL31 at the top of the Trusted SRAM. BL31_BASE is calculated using the - * current BL31 debug size plus a little space for growth. + * Put BL31 at the top of the Trusted SRAM. */ #define BL31_BASE (ARM_BL_RAM_BASE + \ ARM_BL_RAM_SIZE - \ - 0x1D000) + PLAT_ARM_MAX_BL31_SIZE) #define BL31_PROGBITS_LIMIT BL1_RW_BASE #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index 3b6a04ba..e9eebaa0 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -37,11 +37,6 @@ #include <stdint.h> #include <xlat_tables.h> -/* - * Extern declarations common to ARM standard platforms - */ -extern const mmap_region_t plat_arm_mmap[]; - #define ARM_CASSERT_MMAP \ CASSERT((ARRAY_SIZE(plat_arm_mmap) + ARM_BL_REGIONS) \ <= MAX_MMAP_REGIONS, \ @@ -131,9 +126,6 @@ void arm_configure_mmu_el3(unsigned long total_base, #endif /* __ARM_RECOM_STATE_ID_ENC__ */ -/* CCI utility functions */ -void arm_cci_init(void); - /* IO storage utility functions */ void arm_io_setup(void); @@ -187,6 +179,7 @@ int arm_io_is_toc_valid(void); /* * Mandatory functions required in ARM standard platforms */ +unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); void plat_arm_gic_driver_init(void); void plat_arm_gic_init(void); void plat_arm_gic_cpuif_enable(void); @@ -194,6 +187,9 @@ void plat_arm_gic_cpuif_disable(void); void plat_arm_gic_pcpu_init(void); void plat_arm_security_setup(void); void plat_arm_pwrc_setup(void); +void plat_arm_interconnect_init(void); +void plat_arm_interconnect_enter_coherency(void); +void plat_arm_interconnect_exit_coherency(void); /* * Optional functions required in ARM standard platforms @@ -204,6 +200,6 @@ int plat_arm_get_alt_image_source( uintptr_t *dev_handle, uintptr_t *image_spec); unsigned int plat_arm_calc_core_pos(u_register_t mpidr); - +const mmap_region_t *plat_arm_get_mmap(void); #endif /* __PLAT_ARM_H__ */ diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h index c900278b..f92126ba 100644 --- a/include/plat/arm/css/common/css_def.h +++ b/include/plat/arm/css/common/css_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -37,15 +37,12 @@ /************************************************************************* * Definitions common to all ARM Compute SubSystems (CSS) *************************************************************************/ -#define MHU_PAYLOAD_CACHED 0 - #define NSROM_BASE 0x1f000000 #define NSROM_SIZE 0x00001000 /* Following covers CSS Peripherals excluding NSROM and NSRAM */ #define CSS_DEVICE_BASE 0x20000000 #define CSS_DEVICE_SIZE 0x0e000000 -#define MHU_BASE 0x2b1f0000 #define NSRAM_BASE 0x2e000000 #define NSRAM_SIZE 0x00008000 @@ -78,31 +75,47 @@ * SCP <=> AP boot configuration * * The SCP/AP boot configuration is a 32-bit word located at a known offset from - * the start of the Trusted SRAM. Part of this configuration is which CPU is the - * primary, according to the shift and mask definitions below. + * the start of the Trusted SRAM. * * Note that the value stored at this address is only valid at boot time, before * the SCP_BL2 image is transferred to SCP. */ -#define SCP_BOOT_CFG_ADDR (ARM_TRUSTED_SRAM_BASE + 0x80) -#define PRIMARY_CPU_SHIFT 8 -#define PRIMARY_CPU_BIT_WIDTH 4 - -/* - * Base address of the first memory region used for communication between AP - * and SCP. Used by the BOM and SCPI protocols. - * - * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which - * means the SCP/AP configuration data gets overwritten when the AP initiates - * communication with the SCP. - */ -#define SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80) +#define SCP_BOOT_CFG_ADDR PLAT_CSS_SCP_COM_SHARED_MEM_BASE #define CSS_MAP_DEVICE MAP_REGION_FLAT( \ CSS_DEVICE_BASE, \ CSS_DEVICE_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) +/* Platform ID address */ +#define SSC_VERSION_OFFSET 0x040 + +#define SSC_VERSION_CONFIG_SHIFT 28 +#define SSC_VERSION_MAJOR_REV_SHIFT 24 +#define SSC_VERSION_MINOR_REV_SHIFT 20 +#define SSC_VERSION_DESIGNER_ID_SHIFT 12 +#define SSC_VERSION_PART_NUM_SHIFT 0x0 +#define SSC_VERSION_CONFIG_MASK 0xf +#define SSC_VERSION_MAJOR_REV_MASK 0xf +#define SSC_VERSION_MINOR_REV_MASK 0xf +#define SSC_VERSION_DESIGNER_ID_MASK 0xff +#define SSC_VERSION_PART_NUM_MASK 0xfff + +#ifndef __ASSEMBLY__ + +/* SSC_VERSION related accessors */ + +/* Returns the part number of the platform */ +#define GET_SSC_VERSION_PART_NUM(val) \ + (((val) >> SSC_VERSION_PART_NUM_SHIFT) & \ + SSC_VERSION_PART_NUM_MASK) + +/* Returns the configuration number of the platform */ +#define GET_SSC_VERSION_CONFIG(val) \ + (((val) >> SSC_VERSION_CONFIG_SHIFT) & \ + SSC_VERSION_CONFIG_MASK) + +#endif /* __ASSEMBLY__ */ /************************************************************************* * Required platform porting definitions common to all @@ -110,6 +123,13 @@ ************************************************************************/ /* + * The loading of SCP images(SCP_BL2 or SCP_BL2U) is done if there + * respective base addresses are defined (i.e SCP_BL2_BASE, SCP_BL2U_BASE). + * Hence, `CSS_LOAD_SCP_IMAGES` needs to be set to 1 if BL2 needs to load + * an SCP_BL2/SCP_BL2U image. + */ +#if CSS_LOAD_SCP_IMAGES +/* * Load address of SCP_BL2 in CSS platform ports * SCP_BL2 is loaded to the same place as BL31. Once SCP_BL2 is transferred to the * SCP, it is discarded and BL31 is loaded over the top. @@ -117,18 +137,13 @@ #define SCP_BL2_BASE BL31_BASE #define SCP_BL2U_BASE BL31_BASE - -#define PLAT_ARM_SHARED_RAM_CACHED MHU_PAYLOAD_CACHED +#endif /* CSS_LOAD_SCP_IMAGES */ /* Load address of Non-Secure Image for CSS platform ports */ #define PLAT_ARM_NS_IMAGE_OFFSET 0xE0000000 /* TZC related constants */ #define PLAT_ARM_TZC_FILTERS REG_ATTR_FILTER_BIT_ALL -#define PLAT_ARM_TZC_BASE 0x2a4a0000 - -/* System timer related constants */ -#define PLAT_ARM_NSTIMER_FRAME_ID 1 /* Trusted mailbox base address common to all CSS */ #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE |