diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/common/bl_common.h | 42 | ||||
| -rw-r--r-- | include/common/el3_common_macros.S | 24 | ||||
| -rw-r--r-- | include/lib/aarch64/arch.h | 4 | ||||
| -rw-r--r-- | include/lib/aarch64/xlat_tables.h | 42 | ||||
| -rw-r--r-- | include/plat/arm/board/common/board_arm_def.h | 3 | ||||
| -rw-r--r-- | include/plat/arm/common/arm_def.h | 2 | ||||
| -rw-r--r-- | include/plat/common/common_def.h | 11 | ||||
| -rw-r--r-- | include/plat/common/platform.h | 3 |
8 files changed, 80 insertions, 51 deletions
diff --git a/include/common/bl_common.h b/include/common/bl_common.h index e5e6717b..f13dc316 100644 --- a/include/common/bl_common.h +++ b/include/common/bl_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -53,28 +53,12 @@ #define ENTRY_POINT_INFO_ARGS_OFFSET 0x18 /* The following are used to set/get image attributes. */ -#define EXECUTABLE (0x1) -#define NON_EXECUTABLE (0x0) -#define PARAM_EP_EXECUTE_MASK (0x1) -#define PARAM_EP_EXECUTE_SHIFT (0x1) #define PARAM_EP_SECURITY_MASK (0x1) -#define PARAM_EP_SECURITY_SHIFT (0x0) #define GET_SECURITY_STATE(x) (x & PARAM_EP_SECURITY_MASK) #define SET_SECURITY_STATE(x, security) \ ((x) = ((x) & ~PARAM_EP_SECURITY_MASK) | (security)) -#define GET_EXEC_STATE(x) \ - (((x) >> PARAM_EP_EXECUTE_SHIFT) & PARAM_EP_EXECUTE_MASK) - -#define SET_EXEC_STATE(x) \ - (((x) & PARAM_EP_EXECUTE_MASK) << PARAM_EP_EXECUTE_SHIFT) - -#define GET_SEC_STATE(x) \ - (((x) >> PARAM_EP_SECURITY_SHIFT) & PARAM_EP_SECURITY_MASK) - -#define SET_SEC_STATE(x) \ - (((x) & PARAM_EP_SECURITY_MASK) << PARAM_EP_SECURITY_SHIFT) /* * The following are used for image state attributes. @@ -99,11 +83,17 @@ #define EP_GET_ST(x) (x & EP_ST_MASK) #define EP_SET_ST(x, ee) ((x) = ((x) & ~EP_ST_MASK) | (ee)) -#define PARAM_EP 0x01 -#define PARAM_IMAGE_BINARY 0x02 -#define PARAM_BL31 0x03 +#define EP_EXE_MASK 0x8 +#define NON_EXECUTABLE 0x0 +#define EXECUTABLE 0x8 +#define EP_GET_EXE(x) (x & EP_EXE_MASK) +#define EP_SET_EXE(x, ee) ((x) = ((x) & ~EP_EXE_MASK) | (ee)) + +#define PARAM_EP 0x01 +#define PARAM_IMAGE_BINARY 0x02 +#define PARAM_BL31 0x03 -#define VERSION_1 0x01 +#define VERSION_1 0x01 #define INVALID_IMAGE_ID (0xFFFFFFFF) @@ -114,6 +104,14 @@ (_p)->h.attr = (uint32_t)(_attr) ; \ } while (0) +/* Following is used for populating structure members statically. */ +#define SET_STATIC_PARAM_HEAD(_p, _type, _ver, _p_type, _attr) \ + ._p.h.type = (uint8_t)(_type), \ + ._p.h.version = (uint8_t)(_ver), \ + ._p.h.size = (uint16_t)sizeof(_p_type), \ + ._p.h.attr = (uint32_t)(_attr) + + /******************************************************************************* * Constants to indicate type of exception to the common exception handler. ******************************************************************************/ @@ -224,7 +222,6 @@ typedef struct image_info { param_header_t h; uintptr_t image_base; /* physical address of base of image */ uint32_t image_size; /* bytes read from image file */ - uint32_t copied_size; /* image size copied in blocks */ } image_info_t; /***************************************************************************** @@ -238,6 +235,7 @@ typedef struct image_desc { * Refer IMAGE_STATE_XXX defined above. */ unsigned int state; + uint32_t copied_size; /* image size copied in blocks */ image_info_t image_info; entry_point_info_t ep_info; } image_desc_t; diff --git a/include/common/el3_common_macros.S b/include/common/el3_common_macros.S index 6f7136f9..0cd85c34 100644 --- a/include/common/el3_common_macros.S +++ b/include/common/el3_common_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -171,9 +171,19 @@ do_cold_boot: .endif /* _warm_boot_mailbox */ + /* --------------------------------------------------------------------- + * It is a cold boot. + * Perform any processor specific actions upon reset e.g. cache, TLB + * invalidations etc. + * --------------------------------------------------------------------- + */ + bl reset_handler + + el3_arch_init_common \_exception_vectors + .if \_secondary_cold_boot /* ------------------------------------------------------------- - * It is a cold boot. + * Check if this is a primary or secondary CPU cold boot. * The primary CPU will set up the platform while the * secondaries are placed in a platform-specific state until the * primary CPU performs the necessary actions to bring them out @@ -186,20 +196,16 @@ /* This is a cold boot on a secondary CPU */ bl plat_secondary_cold_boot_setup /* plat_secondary_cold_boot_setup() is not supposed to return */ - secondary_panic: - b secondary_panic + bl el3_panic do_primary_cold_boot: .endif /* _secondary_cold_boot */ /* --------------------------------------------------------------------- - * Perform any processor specific actions upon reset e.g. cache, TLB - * invalidations etc. + * Initialize memory now. Secondary CPU initialization won't get to this + * point. * --------------------------------------------------------------------- */ - bl reset_handler - - el3_arch_init_common \_exception_vectors .if \_init_memory bl platform_mem_init diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 49efafc5..a9b2dbb2 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -419,11 +419,11 @@ #define AP_RW (0x0 << 5) #define NS (0x1 << 3) -#define ATTR_SO_INDEX 0x2 +#define ATTR_NON_CACHEABLE_INDEX 0x2 #define ATTR_DEVICE_INDEX 0x1 #define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0 #define LOWER_ATTRS(x) (((x) & 0xfff) << 2) -#define ATTR_SO (0x0) +#define ATTR_NON_CACHEABLE (0x44) #define ATTR_DEVICE (0x4) #define ATTR_IWBWA_OWBWA_NTR (0xff) #define MAIR_ATTR_SET(attr, index) (attr << (index << 3)) diff --git a/include/lib/aarch64/xlat_tables.h b/include/lib/aarch64/xlat_tables.h index 0b5dbdf2..d21100e3 100644 --- a/include/lib/aarch64/xlat_tables.h +++ b/include/lib/aarch64/xlat_tables.h @@ -52,21 +52,41 @@ #define MAP_REGION(pa, va, sz, attr) {(pa), (va), (sz), (attr)} /* - * Flags for building up memory mapping attributes. - * These are organised so that a clear bit gives a more restrictive mapping - * that a set bit, that way a bitwise-and two sets of attributes will never give - * an attribute which has greater access rights that any of the original - * attributes. + * Shifts and masks to access fields of an mmap_attr_t + */ +#define MT_TYPE_MASK 0x7 +#define MT_TYPE(_attr) ((_attr) & MT_TYPE_MASK) +/* Access permissions (RO/RW) */ +#define MT_PERM_SHIFT 3 +/* Security state (SECURE/NS) */ +#define MT_SEC_SHIFT 4 + +/* + * Memory mapping attributes */ typedef enum { - MT_DEVICE = 0 << 0, - MT_MEMORY = 1 << 0, + /* + * Memory types supported. + * These are organised so that, going down the list, the memory types + * are getting weaker; conversely going up the list the memory types are + * getting stronger. + */ + MT_DEVICE, + MT_NON_CACHEABLE, + MT_MEMORY, + /* Values up to 7 are reserved to add new memory types in the future */ - MT_RO = 0 << 1, - MT_RW = 1 << 1, + /* + * The following values are organised so that a clear bit gives a more + * restrictive mapping than a set bit, that way a bitwise-and of two + * sets of attributes will never give an attribute which has greater + * access rights than any of the original attributes. + */ + MT_RO = 0 << MT_PERM_SHIFT, + MT_RW = 1 << MT_PERM_SHIFT, - MT_SECURE = 0 << 2, - MT_NS = 1 << 2 + MT_SECURE = 0 << MT_SEC_SHIFT, + MT_NS = 1 << MT_SEC_SHIFT, } mmap_attr_t; /* diff --git a/include/plat/arm/board/common/board_arm_def.h b/include/plat/arm/board/common/board_arm_def.h index aaf419e2..b065537d 100644 --- a/include/plat/arm/board/common/board_arm_def.h +++ b/include/plat/arm/board/common/board_arm_def.h @@ -91,5 +91,8 @@ #define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE #define PLAT_ARM_FIP_MAX_SIZE V2M_FLASH0_SIZE +#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE +#define PLAT_ARM_NVM_SIZE V2M_FLASH0_SIZE + #endif /* __BOARD_ARM_DEF_H__ */ diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index dab75450..d04f9d6f 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -294,7 +294,7 @@ #define BL2U_BASE BL2_BASE #define BL2U_LIMIT BL31_BASE #define NS_BL2U_BASE ARM_NS_DRAM1_BASE -#define NS_BL1U_BASE (V2M_FLASH0_BASE + 0x03EB8000) +#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + 0x03EB8000) /* * ID of the secure physical generic timer interrupt used by the TSP. diff --git a/include/plat/common/common_def.h b/include/plat/common/common_def.h index 916720c5..9fac9fa2 100644 --- a/include/plat/common/common_def.h +++ b/include/plat/common/common_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -72,11 +72,12 @@ #define BL2_IMAGE_DESC { \ .image_id = BL2_IMAGE_ID, \ - .image_info.h.version = VERSION_1, \ - .image_info.h.attr = SET_EXEC_STATE(EXECUTABLE),\ + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, \ + VERSION_1, image_info_t, 0), \ .image_info.image_base = BL2_BASE, \ - .ep_info.h.attr = SET_SEC_STATE(SECURE), \ - .ep_info.pc = BL2_BASE \ + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, \ + VERSION_1, entry_point_info_t, SECURE | EXECUTABLE),\ + .ep_info.pc = BL2_BASE, \ } #endif /* __COMMON_DEF_H__ */ diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h index f37a80f3..5c61f381 100644 --- a/include/plat/common/platform.h +++ b/include/plat/common/platform.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -83,6 +83,7 @@ void plat_report_exception(unsigned long); int plat_crash_console_init(void); int plat_crash_console_putc(int c); void plat_error_handler(int err) __dead2; +void plat_panic_handler(void) __dead2; /******************************************************************************* * Mandatory BL1 functions |