diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/common/asm_macros.S | 24 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a53.h | 10 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a57.h | 10 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a72.h | 10 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a73.h | 5 |
5 files changed, 55 insertions, 4 deletions
diff --git a/include/common/asm_macros.S b/include/common/asm_macros.S index d4bd11ee..bd8bb709 100644 --- a/include/common/asm_macros.S +++ b/include/common/asm_macros.S @@ -148,17 +148,33 @@ #endif /* + * Helper assembler macro to count trailing zeros. The output is + * populated in the `TZ_COUNT` symbol. + */ + .macro count_tz _value, _tz_count + .if \_value + count_tz "(\_value >> 1)", "(\_tz_count + 1)" + .else + .equ TZ_COUNT, (\_tz_count - 1) + .endif + .endm + + /* * This macro declares an array of 1 or more stacks, properly * aligned and in the requested section */ -#define STACK_ALIGN 6 +#define DEFAULT_STACK_ALIGN (1 << 6) /* In case the caller doesnt provide alignment */ - .macro declare_stack _name, _section, _size, _count - .if ((\_size & ((1 << STACK_ALIGN) - 1)) <> 0) + .macro declare_stack _name, _section, _size, _count, _align=DEFAULT_STACK_ALIGN + count_tz \_align, 0 + .if (\_align - (1 << TZ_COUNT)) + .error "Incorrect stack alignment specified (Must be a power of 2)." + .endif + .if ((\_size & ((1 << TZ_COUNT) - 1)) <> 0) .error "Stack size not correctly aligned" .endif .section \_section, "aw", %nobits - .align STACK_ALIGN + .align TZ_COUNT \_name: .space ((\_count) * (\_size)), 0 .endm diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h index 169d8f4b..6976b809 100644 --- a/include/lib/cpus/aarch64/cortex_a53.h +++ b/include/lib/cpus/aarch64/cortex_a53.h @@ -57,6 +57,11 @@ #define CPUECTLR_FPU_RET_CTRL_MASK (0x7 << CPUECTLR_FPU_RET_CTRL_SHIFT) /******************************************************************************* + * CPU Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */ + +/******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ #define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ @@ -79,4 +84,9 @@ #define L2ECTLR_RET_CTRL_SHIFT 0 #define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ + #endif /* __CORTEX_A53_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index ac4ae570..c5a218b7 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -57,6 +57,11 @@ #define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT) /******************************************************************************* + * CPU Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */ + +/******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ #define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ @@ -90,4 +95,9 @@ #define L2ECTLR_RET_CTRL_SHIFT 0 #define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ + #endif /* __CORTEX_A57_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h index fa10ca90..01edf43b 100644 --- a/include/lib/cpus/aarch64/cortex_a72.h +++ b/include/lib/cpus/aarch64/cortex_a72.h @@ -45,6 +45,11 @@ #define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) /******************************************************************************* + * CPU Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */ + +/******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ #define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ @@ -65,4 +70,9 @@ #define L2_TAG_RAM_LATENCY_2_CYCLES 0x1 #define L2_TAG_RAM_LATENCY_3_CYCLES 0x2 +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ + #endif /* __CORTEX_A72_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h index 2ad04677..13e114a3 100644 --- a/include/lib/cpus/aarch64/cortex_a73.h +++ b/include/lib/cpus/aarch64/cortex_a73.h @@ -41,4 +41,9 @@ #define CORTEX_A73_CPUECTLR_SMP_BIT (1 << 6) +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CORTEX_A73_L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ + #endif /* __CORTEX_A73_H__ */ |