diff options
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/cpus/aarch64/cortex_a53.S | 88 | ||||
| -rw-r--r-- | lib/cpus/aarch64/denver.S | 166 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk | 17 |
3 files changed, 268 insertions, 3 deletions
diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S index e149e6e6..e4b94e80 100644 --- a/lib/cpus/aarch64/cortex_a53.S +++ b/lib/cpus/aarch64/cortex_a53.S @@ -59,11 +59,93 @@ func cortex_a53_disable_smp ret endfunc cortex_a53_disable_smp + /* -------------------------------------------------- + * Errata Workaround for Cortex A53 Errata #826319. + * This applies only to revision <= r0p2 of Cortex A53. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * -------------------------------------------------- + */ +func errata_a53_826319_wa + /* + * Compare x0 against revision r0p2 + */ + cmp x0, #2 + b.ls apply_826319 +#if DEBUG + b print_revision_warning +#else + ret +#endif +apply_826319: + mrs x1, L2ACTLR_EL1 + bic x1, x1, #L2ACTLR_ENABLE_UNIQUECLEAN + orr x1, x1, #L2ACTLR_DISABLE_CLEAN_PUSH + msr L2ACTLR_EL1, x1 + ret +endfunc errata_a53_826319_wa + + /* -------------------------------------------------- + * Errata Workaround for Cortex A53 Errata #836870. + * This applies only to revision <= r0p3 of Cortex A53. + * From r0p4 and onwards, this errata is enabled by + * default. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * -------------------------------------------------- + */ +func errata_a53_836870_wa + /* + * Compare x0 against revision r0p3 + */ + cmp x0, #3 + b.ls apply_836870 +#if DEBUG + b print_revision_warning +#else + ret +#endif +apply_836870: + mrs x1, CPUACTLR_EL1 + orr x1, x1, #CPUACTLR_DTAH + msr CPUACTLR_EL1, x1 + ret +endfunc errata_a53_836870_wa + + /* ------------------------------------------------- + * The CPU Ops reset function for Cortex-A53. + * Clobbers: x0-x5, x15, x19, x30 + * ------------------------------------------------- + */ func cortex_a53_reset_func + mov x19, x30 + mrs x0, midr_el1 + + /* + * Extract the variant[20:23] and revision[0:3] from x0 + * and pack it in x15[0:7] as variant[4:7] and revision[0:3]. + * First extract x0[16:23] to x15[0:7] and zero fill the rest. + * Then extract x0[0:3] into x15[0:3] retaining other bits. + */ + ubfx x15, x0, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), \ + #(MIDR_REV_BITS + MIDR_VAR_BITS) + bfxil x15, x0, #MIDR_REV_SHIFT, #MIDR_REV_BITS + +#if ERRATA_A53_826319 + mov x0, x15 + bl errata_a53_826319_wa +#endif + +#if ERRATA_A53_836870 + mov x0, x15 + bl errata_a53_836870_wa +#endif + /* --------------------------------------------- * As a bare minimum enable the SMP bit if it is * not already set. - * Clobbers : x0 * --------------------------------------------- */ mrs x0, CPUECTLR_EL1 @@ -71,9 +153,9 @@ func cortex_a53_reset_func b.ne skip_smp_setup orr x0, x0, #CPUECTLR_SMP_BIT msr CPUECTLR_EL1, x0 - isb skip_smp_setup: - ret + isb + ret x19 endfunc cortex_a53_reset_func func cortex_a53_core_pwr_dwn diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S new file mode 100644 index 00000000..bce05737 --- /dev/null +++ b/lib/cpus/aarch64/denver.S @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch.h> +#include <asm_macros.S> +#include <assert_macros.S> +#include <denver.h> +#include <cpu_macros.S> +#include <plat_macros.S> + + /* --------------------------------------------- + * Disable debug interfaces + * --------------------------------------------- + */ +func denver_disable_ext_debug + mov x0, #1 + msr osdlr_el1, x0 + isb + dsb sy + ret +endfunc denver_disable_ext_debug + + /* ---------------------------------------------------- + * Enable dynamic code optimizer (DCO) + * ---------------------------------------------------- + */ +func denver_enable_dco + mrs x0, mpidr_el1 + and x0, x0, #0xF + mov x1, #1 + lsl x1, x1, x0 + msr s3_0_c15_c0_2, x1 + isb + ret +endfunc denver_enable_dco + + /* ---------------------------------------------------- + * Disable dynamic code optimizer (DCO) + * ---------------------------------------------------- + */ +func denver_disable_dco + + /* turn off background work */ + mrs x0, mpidr_el1 + and x0, x0, #0xF + mov x1, #1 + lsl x1, x1, x0 + lsl x2, x1, #16 + msr s3_0_c15_c0_2, x2 + isb + + /* wait till the background work turns off */ +1: mrs x2, s3_0_c15_c0_2 + lsr x2, x2, #32 + and w2, w2, 0xFFFF + and x2, x2, x1 + cbnz x2, 1b + + ret +endfunc denver_disable_dco + + /* ------------------------------------------------- + * The CPU Ops reset function for Denver. + * ------------------------------------------------- + */ +func denver_reset_func + + mov x19, x30 + + /* ---------------------------------------------------- + * Enable dynamic code optimizer (DCO) + * ---------------------------------------------------- + */ + bl denver_enable_dco + + ret x19 +endfunc denver_reset_func + + /* ---------------------------------------------------- + * The CPU Ops core power down function for Denver. + * ---------------------------------------------------- + */ +func denver_core_pwr_dwn + + mov x19, x30 + + /* ---------------------------------------------------- + * We enter the 'core power gated with ARM state not + * retained' power state during CPU power down. We let + * DCO know that we expect to enter this power state + * by writing to the ACTLR_EL1 register. + * ---------------------------------------------------- + */ + mov x0, #DENVER_CPU_STATE_POWER_DOWN + msr actlr_el1, x0 + + /* --------------------------------------------- + * Force DCO to be quiescent + * --------------------------------------------- + */ + bl denver_disable_dco + + /* --------------------------------------------- + * Force the debug interfaces to be quiescent + * --------------------------------------------- + */ + bl denver_disable_ext_debug + + ret x19 +endfunc denver_core_pwr_dwn + + /* ------------------------------------------------------- + * The CPU Ops cluster power down function for Denver. + * ------------------------------------------------------- + */ +func denver_cluster_pwr_dwn + ret +endfunc denver_cluster_pwr_dwn + + /* --------------------------------------------- + * This function provides Denver specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.denver_regs, "aS" +denver_regs: /* The ascii list of register names to be reported */ + .asciz "actlr_el1", "" + +func denver_cpu_reg_dump + adr x6, denver_regs + mrs x8, ACTLR_EL1 + ret +endfunc denver_cpu_reg_dump + +declare_cpu_ops denver, DENVER_1_0_MIDR diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 1c5512e9..a872360e 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -40,6 +40,15 @@ $(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN)) # CPU Errata Build flags. These should be enabled by the # platform if the errata needs to be applied. +# Flag to apply errata 826319 during reset. This errata applies only to +# revision <= r0p2 of the Cortex A53 cpu. +ERRATA_A53_826319 ?=0 + +# Flag to apply errata 836870 during reset. This errata applies only to +# revision <= r0p3 of the Cortex A53 cpu. From r0p4 and onwards, this +# errata is enabled by default. +ERRATA_A53_836870 ?=0 + # Flag to apply errata 806969 during reset. This errata applies only to # revision r0p0 of the Cortex A57 cpu. ERRATA_A57_806969 ?=0 @@ -48,6 +57,14 @@ ERRATA_A57_806969 ?=0 # revision r0p0 of the Cortex A57 cpu. ERRATA_A57_813420 ?=0 +# Process ERRATA_A53_826319 flag +$(eval $(call assert_boolean,ERRATA_A53_826319)) +$(eval $(call add_define,ERRATA_A53_826319)) + +# Process ERRATA_A53_836870 flag +$(eval $(call assert_boolean,ERRATA_A53_836870)) +$(eval $(call add_define,ERRATA_A53_836870)) + # Process ERRATA_A57_806969 flag $(eval $(call assert_boolean,ERRATA_A57_806969)) $(eval $(call add_define,ERRATA_A57_806969)) |