diff options
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/cpus/aarch64/cortex_a35.S | 6 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a53.S | 39 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a57.S | 58 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cpu_helpers.S | 17 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk | 18 | ||||
| -rw-r--r-- | lib/stdlib/std.c | 45 |
6 files changed, 84 insertions, 99 deletions
diff --git a/lib/cpus/aarch64/cortex_a35.S b/lib/cpus/aarch64/cortex_a35.S index 6a447c01..ba29d6d4 100644 --- a/lib/cpus/aarch64/cortex_a35.S +++ b/lib/cpus/aarch64/cortex_a35.S @@ -67,16 +67,12 @@ endfunc cortex_a35_disable_smp */ func cortex_a35_reset_func /* --------------------------------------------- - * As a bare minimum enable the SMP bit if it is - * not already set. + * Enable the SMP bit. * --------------------------------------------- */ mrs x0, CORTEX_A35_CPUECTLR_EL1 - tst x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT - b.ne skip_smp_setup orr x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT msr CORTEX_A35_CPUECTLR_EL1, x0 -skip_smp_setup: isb ret endfunc cortex_a35_reset_func diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S index e4b94e80..c33ba571 100644 --- a/lib/cpus/aarch64/cortex_a53.S +++ b/lib/cpus/aarch64/cortex_a53.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -86,33 +86,40 @@ apply_826319: ret endfunc errata_a53_826319_wa - /* -------------------------------------------------- - * Errata Workaround for Cortex A53 Errata #836870. - * This applies only to revision <= r0p3 of Cortex A53. - * From r0p4 and onwards, this errata is enabled by - * default. + /* --------------------------------------------------------------------- + * Disable the cache non-temporal hint. + * + * This ignores the Transient allocation hint in the MAIR and treats + * allocations the same as non-transient allocation types. As a result, + * the LDNP and STNP instructions in AArch64 behave the same as the + * equivalent LDP and STP instructions. + * + * This is relevant only for revisions <= r0p3 of Cortex-A53. + * From r0p4 and onwards, the bit to disable the hint is enabled by + * default at reset. + * * Inputs: * x0: variant[4:7] and revision[0:3] of current cpu. * Clobbers : x0 - x5 - * -------------------------------------------------- + * --------------------------------------------------------------------- */ -func errata_a53_836870_wa +func a53_disable_non_temporal_hint /* * Compare x0 against revision r0p3 */ cmp x0, #3 - b.ls apply_836870 + b.ls disable_hint #if DEBUG b print_revision_warning #else ret #endif -apply_836870: +disable_hint: mrs x1, CPUACTLR_EL1 orr x1, x1, #CPUACTLR_DTAH msr CPUACTLR_EL1, x1 ret -endfunc errata_a53_836870_wa +endfunc a53_disable_non_temporal_hint /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A53. @@ -138,22 +145,18 @@ func cortex_a53_reset_func bl errata_a53_826319_wa #endif -#if ERRATA_A53_836870 +#if ERRATA_A53_836870 || A53_DISABLE_NON_TEMPORAL_HINT mov x0, x15 - bl errata_a53_836870_wa + bl a53_disable_non_temporal_hint #endif /* --------------------------------------------- - * As a bare minimum enable the SMP bit if it is - * not already set. + * Enable the SMP bit. * --------------------------------------------- */ mrs x0, CPUECTLR_EL1 - tst x0, #CPUECTLR_SMP_BIT - b.ne skip_smp_setup orr x0, x0, #CPUECTLR_SMP_BIT msr CPUECTLR_EL1, x0 -skip_smp_setup: isb ret x19 endfunc cortex_a53_reset_func diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index 05799d61..99db25b8 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -105,17 +105,9 @@ func errata_a57_806969_wa ret #endif apply_806969: - /* - * Test if errata has already been applied in an earlier - * invocation of the reset handler and does not need to - * be applied again. - */ mrs x1, CPUACTLR_EL1 - tst x1, #CPUACTLR_NO_ALLOC_WBWA - b.ne skip_806969 orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA msr CPUACTLR_EL1, x1 -skip_806969: ret endfunc errata_a57_806969_wa @@ -139,20 +131,41 @@ func errata_a57_813420_wa ret #endif apply_813420: - /* - * Test if errata has already been applied in an earlier - * invocation of the reset handler and does not need to - * be applied again. - */ mrs x1, CPUACTLR_EL1 - tst x1, #CPUACTLR_DCC_AS_DCCI - b.ne skip_813420 orr x1, x1, #CPUACTLR_DCC_AS_DCCI msr CPUACTLR_EL1, x1 -skip_813420: ret endfunc errata_a57_813420_wa + /* -------------------------------------------------------------------- + * Disable the over-read from the LDNP instruction. + * + * This applies to all revisions <= r1p2. The performance degradation + * observed with LDNP/STNP has been fixed on r1p3 and onwards. + * + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5, x30 + * --------------------------------------------------------------------- + */ +func a57_disable_ldnp_overread + /* + * Compare x0 against revision r1p2 + */ + cmp x0, #0x12 + b.ls disable_hint +#if DEBUG + b print_revision_warning +#else + ret +#endif +disable_hint: + mrs x1, CPUACTLR_EL1 + orr x1, x1, #CPUACTLR_DIS_OVERREAD + msr CPUACTLR_EL1, x1 + ret +endfunc a57_disable_ldnp_overread + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A57. * Clobbers: x0-x5, x15, x19, x30 @@ -181,17 +194,18 @@ func cortex_a57_reset_func bl errata_a57_813420_wa #endif +#if A57_DISABLE_NON_TEMPORAL_HINT + mov x0, x15 + bl a57_disable_ldnp_overread +#endif + /* --------------------------------------------- - * As a bare minimum enable the SMP bit if it is - * not already set. + * Enable the SMP bit. * --------------------------------------------- */ mrs x0, CPUECTLR_EL1 - tst x0, #CPUECTLR_SMP_BIT - b.ne skip_smp_setup orr x0, x0, #CPUECTLR_SMP_BIT msr CPUECTLR_EL1, x0 -skip_smp_setup: isb ret x19 endfunc cortex_a57_reset_func diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S index e8a13929..e41d95ba 100644 --- a/lib/cpus/aarch64/cpu_helpers.S +++ b/lib/cpus/aarch64/cpu_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -205,16 +205,17 @@ error_exit: endfunc get_cpu_ops_ptr #if DEBUG - /* - * This function prints a warning message to the crash console - * if the CPU revision/part number does not match the errata - * workaround enabled in the build. - * Clobber: x30, x0 - x5 - */ .section .rodata.rev_warn_str, "aS" rev_warn_str: - .asciz "Warning: Skipping Errata workaround for non matching CPU revision number.\n" + .asciz "Warning: Skipping CPU specific reset operation for non-matching CPU revision number.\n" + /* + * This function prints the above warning message to the crash console. + * It should be called when a CPU specific operation is enabled in the + * build but doesn't apply to this CPU revision/part number. + * + * Clobber: x30, x0 - x5 + */ .globl print_revision_warning func print_revision_warning mov x5, x30 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index a872360e..a3a08e15 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: @@ -32,10 +32,26 @@ # cluster is powered down. SKIP_A57_L1_FLUSH_PWR_DWN ?=0 +# Flag to disable the cache non-temporal hint. +# It is enabled by default. +A53_DISABLE_NON_TEMPORAL_HINT ?=1 + +# Flag to disable the cache non-temporal hint. +# It is enabled by default. +A57_DISABLE_NON_TEMPORAL_HINT ?=1 + # Process SKIP_A57_L1_FLUSH_PWR_DWN flag $(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN)) $(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN)) +# Process A53_DISABLE_NON_TEMPORAL_HINT flag +$(eval $(call assert_boolean,A53_DISABLE_NON_TEMPORAL_HINT)) +$(eval $(call add_define,A53_DISABLE_NON_TEMPORAL_HINT)) + +# Process A57_DISABLE_NON_TEMPORAL_HINT flag +$(eval $(call assert_boolean,A57_DISABLE_NON_TEMPORAL_HINT)) +$(eval $(call add_define,A57_DISABLE_NON_TEMPORAL_HINT)) + # CPU Errata Build flags. These should be enabled by the # platform if the errata needs to be applied. diff --git a/lib/stdlib/std.c b/lib/stdlib/std.c deleted file mode 100644 index 5f6ef752..00000000 --- a/lib/stdlib/std.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - - -/* Include the various implemented functions */ -#include "abort.c" -#include "assert.c" -#include "exit.c" -#include "mem.c" -#include "printf.c" -#include "putchar.c" -#include "puts.c" -#include "sscanf.c" -#include "strchr.c" -#include "strcmp.c" -#include "strlen.c" -#include "strncmp.c" -#include "subr_prf.c" |