diff options
Diffstat (limited to 'plat/arm/common')
| -rw-r--r-- | plat/arm/common/aarch64/arm_common.c | 17 | ||||
| -rw-r--r-- | plat/arm/common/arm_bl31_setup.c | 11 | ||||
| -rw-r--r-- | plat/arm/common/arm_pm.c | 22 |
3 files changed, 40 insertions, 10 deletions
diff --git a/plat/arm/common/aarch64/arm_common.c b/plat/arm/common/aarch64/arm_common.c index 48b4ac80..42641837 100644 --- a/plat/arm/common/aarch64/arm_common.c +++ b/plat/arm/common/aarch64/arm_common.c @@ -32,6 +32,7 @@ #include <cci.h> #include <mmio.h> #include <plat_arm.h> +#include <platform_def.h> #include <xlat_tables.h> @@ -142,3 +143,19 @@ void arm_cci_init(void) { cci_init(PLAT_ARM_CCI_BASE, cci_map, ARRAY_SIZE(cci_map)); } + +/******************************************************************************* + * Configures access to the system counter timer module. + ******************************************************************************/ +void arm_configure_sys_timer(void) +{ + unsigned int reg_val; + + reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); + reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); + reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); + mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); + + reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); + mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); +} diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c index 899463ee..923c333c 100644 --- a/plat/arm/common/arm_bl31_setup.c +++ b/plat/arm/common/arm_bl31_setup.c @@ -40,7 +40,6 @@ #include <mmio.h> #include <plat_arm.h> #include <platform.h> -#include <platform_def.h> /* @@ -197,8 +196,6 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, ******************************************************************************/ void arm_bl31_platform_setup(void) { - unsigned int reg_val; - /* Initialize the gic cpu and distributor interfaces */ plat_arm_gic_init(); arm_gic_setup(); @@ -217,13 +214,7 @@ void arm_bl31_platform_setup(void) CNTCR_FCREQ(0) | CNTCR_EN); /* Allow access to the System counter timer module */ - reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); - reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); - reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); - mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); - - reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); - mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); + arm_configure_sys_timer(); /* Initialize power controller before setting up topology */ plat_arm_pwrc_setup(); diff --git a/plat/arm/common/arm_pm.c b/plat/arm/common/arm_pm.c index 2497588f..d13d2683 100644 --- a/plat/arm/common/arm_pm.c +++ b/plat/arm/common/arm_pm.c @@ -30,7 +30,9 @@ #include <arch_helpers.h> #include <arm_def.h> +#include <arm_gic.h> #include <assert.h> +#include <console.h> #include <errno.h> #include <plat_arm.h> #include <platform_def.h> @@ -148,6 +150,26 @@ int arm_validate_ns_entrypoint(uintptr_t entrypoint) return PSCI_E_INVALID_ADDRESS; } +/****************************************************************************** + * Helper function to resume the platform from system suspend. Reinitialize + * the system components which are not in the Always ON power domain. + * TODO: Unify the platform setup when waking up from cold boot and system + * resume in arm_bl31_platform_setup(). + *****************************************************************************/ +void arm_system_pwr_domain_resume(void) +{ + console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, + ARM_CONSOLE_BAUDRATE); + + /* Assert system power domain is available on the platform */ + assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); + + arm_gic_setup(); + plat_arm_security_setup(); + + arm_configure_sys_timer(); +} + /******************************************************************************* * Private function to program the mailbox for a cpu before it is released * from reset. This function assumes that the Trusted mail box base is within |