diff options
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/arm/board/common/board_css_common.c | 8 | ||||
| -rw-r--r-- | plat/arm/board/fvp/fvp_common.c | 9 | ||||
| -rw-r--r-- | plat/arm/common/aarch64/arm_common.c | 104 | ||||
| -rw-r--r-- | plat/arm/common/arm_bl1_setup.c | 11 | ||||
| -rw-r--r-- | plat/arm/common/arm_bl2_setup.c | 19 | ||||
| -rw-r--r-- | plat/arm/common/arm_bl2u_setup.c | 21 | ||||
| -rw-r--r-- | plat/arm/common/arm_bl31_setup.c | 27 | ||||
| -rw-r--r-- | plat/arm/common/arm_cci.c | 1 | ||||
| -rw-r--r-- | plat/arm/common/arm_common.mk | 5 | ||||
| -rw-r--r-- | plat/arm/common/arm_io_storage.c | 4 | ||||
| -rw-r--r-- | plat/arm/common/tsp/arm_tsp_setup.c | 23 | ||||
| -rw-r--r-- | plat/mediatek/mt8173/aarch64/platform_common.c | 3 | ||||
| -rw-r--r-- | plat/mediatek/mt8173/plat_mt_gic.c | 3 | ||||
| -rw-r--r-- | plat/rockchip/common/aarch64/platform_common.c | 1 | ||||
| -rw-r--r-- | plat/rockchip/common/rockchip_gicv2.c | 1 | ||||
| -rw-r--r-- | plat/rockchip/common/rockchip_gicv3.c | 1 | ||||
| -rw-r--r-- | plat/xilinx/zynqmp/bl31_zynqmp_setup.c | 8 | ||||
| -rw-r--r-- | plat/xilinx/zynqmp/pm_service/pm_client.c | 3 | ||||
| -rw-r--r-- | plat/xilinx/zynqmp/tsp/tsp_plat_setup.c | 9 |
19 files changed, 135 insertions, 126 deletions
diff --git a/plat/arm/board/common/board_css_common.c b/plat/arm/board/common/board_css_common.c index 62253f8c..69b744d9 100644 --- a/plat/arm/board/common/board_css_common.c +++ b/plat/arm/board/common/board_css_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -31,9 +31,9 @@ #include <plat_arm.h> /* - * Table of regions for different BL stages to map using the MMU. - * This doesn't include Trusted RAM as the 'mem_layout' argument passed to - * arm_configure_mmu_elx() will give the available subset of that, + * Table of memory regions for different BL stages to map using the MMU. + * This doesn't include Trusted SRAM as arm_setup_page_tables() already + * takes care of mapping it. */ #if IMAGE_BL1 const mmap_region_t plat_arm_mmap[] = { diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c index 0f557af2..002cff67 100644 --- a/plat/arm/board/fvp/fvp_common.c +++ b/plat/arm/board/fvp/fvp_common.c @@ -66,9 +66,12 @@ arm_config_t arm_config; /* - * Table of regions for various BL stages to map using the MMU. - * This doesn't include TZRAM as the 'mem_layout' argument passed to - * arm_configure_mmu_elx() will give the available subset of that, + * Table of memory regions for various BL stages to map using the MMU. + * This doesn't include Trusted SRAM as arm_setup_page_tables() already + * takes care of mapping it. + * + * The flash needs to be mapped as writable in order to erase the FIP's Table of + * Contents in case of unrecoverable error (see plat_error_handler()). */ #if IMAGE_BL1 const mmap_region_t plat_arm_mmap[] = { diff --git a/plat/arm/common/aarch64/arm_common.c b/plat/arm/common/aarch64/arm_common.c index c4cc80e6..7c0b93db 100644 --- a/plat/arm/common/aarch64/arm_common.c +++ b/plat/arm/common/aarch64/arm_common.c @@ -50,57 +50,67 @@ extern const mmap_region_t plat_arm_mmap[]; #pragma weak plat_get_syscnt_freq #endif -/******************************************************************************* - * Macro generating the code for the function setting up the pagetables as per - * the platform memory map & initialize the mmu, for the given exception level - ******************************************************************************/ +/* + * Set up the page tables for the generic and platform-specific memory regions. + * The extents of the generic memory regions are specified by the function + * arguments and consist of: + * - Trusted SRAM seen by the BL image; + * - Code section; + * - Read-only data section; + * - Coherent memory region, if applicable. + */ +void arm_setup_page_tables(unsigned long total_base, + unsigned long total_size, + unsigned long code_start, + unsigned long code_limit, + unsigned long rodata_start, + unsigned long rodata_limit #if USE_COHERENT_MEM -#define DEFINE_CONFIGURE_MMU_EL(_el) \ - void arm_configure_mmu_el##_el(unsigned long total_base, \ - unsigned long total_size, \ - unsigned long ro_start, \ - unsigned long ro_limit, \ - unsigned long coh_start, \ - unsigned long coh_limit) \ - { \ - mmap_add_region(total_base, total_base, \ - total_size, \ - MT_MEMORY | MT_RW | MT_SECURE); \ - mmap_add_region(ro_start, ro_start, \ - ro_limit - ro_start, \ - MT_MEMORY | MT_RO | MT_SECURE); \ - mmap_add_region(coh_start, coh_start, \ - coh_limit - coh_start, \ - MT_DEVICE | MT_RW | MT_SECURE); \ - mmap_add(plat_arm_get_mmap()); \ - init_xlat_tables(); \ - \ - enable_mmu_el##_el(0); \ - } -#else -#define DEFINE_CONFIGURE_MMU_EL(_el) \ - void arm_configure_mmu_el##_el(unsigned long total_base, \ - unsigned long total_size, \ - unsigned long ro_start, \ - unsigned long ro_limit) \ - { \ - mmap_add_region(total_base, total_base, \ - total_size, \ - MT_MEMORY | MT_RW | MT_SECURE); \ - mmap_add_region(ro_start, ro_start, \ - ro_limit - ro_start, \ - MT_MEMORY | MT_RO | MT_SECURE); \ - mmap_add(plat_arm_get_mmap()); \ - init_xlat_tables(); \ - \ - enable_mmu_el##_el(0); \ - } + , + unsigned long coh_start, + unsigned long coh_limit +#endif + ) +{ + /* + * Map the Trusted SRAM with appropriate memory attributes. + * Subsequent mappings will adjust the attributes for specific regions. + */ + VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n", + (void *) total_base, (void *) (total_base + total_size)); + mmap_add_region(total_base, total_base, + total_size, + MT_MEMORY | MT_RW | MT_SECURE); + + /* Re-map the code section */ + VERBOSE("Code region: %p - %p\n", + (void *) code_start, (void *) code_limit); + mmap_add_region(code_start, code_start, + code_limit - code_start, + MT_CODE | MT_SECURE); + + /* Re-map the read-only data section */ + VERBOSE("Read-only data region: %p - %p\n", + (void *) rodata_start, (void *) rodata_limit); + mmap_add_region(rodata_start, rodata_start, + rodata_limit - rodata_start, + MT_RO_DATA | MT_SECURE); + +#if USE_COHERENT_MEM + /* Re-map the coherent memory region */ + VERBOSE("Coherent region: %p - %p\n", + (void *) coh_start, (void *) coh_limit); + mmap_add_region(coh_start, coh_start, + coh_limit - coh_start, + MT_DEVICE | MT_RW | MT_SECURE); #endif -/* Define EL1 and EL3 variants of the function initialising the MMU */ -DEFINE_CONFIGURE_MMU_EL(1) -DEFINE_CONFIGURE_MMU_EL(3) + /* Now (re-)map the platform-specific memory regions */ + mmap_add(plat_arm_get_mmap()); + /* Create the page tables to reflect the above mappings */ + init_xlat_tables(); +} uintptr_t plat_get_ns_image_entrypoint(void) { diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c index 951f48a5..c94f0cd7 100644 --- a/plat/arm/common/arm_bl1_setup.c +++ b/plat/arm/common/arm_bl1_setup.c @@ -35,6 +35,8 @@ #include <platform_def.h> #include <plat_arm.h> #include <sp805.h> +#include <utils.h> +#include <xlat_tables.h> #include "../../../bl1/bl1_private.h" @@ -118,15 +120,18 @@ void bl1_early_platform_setup(void) *****************************************************************************/ void arm_bl1_plat_arch_setup(void) { - arm_configure_mmu_el3(bl1_tzram_layout.total_base, + arm_setup_page_tables(bl1_tzram_layout.total_base, bl1_tzram_layout.total_size, - BL1_RO_BASE, - BL1_RO_LIMIT + BL_CODE_BASE, + BL1_CODE_LIMIT, + BL1_RO_DATA_BASE, + BL1_RO_DATA_LIMIT #if USE_COHERENT_MEM , BL1_COHERENT_RAM_BASE, BL1_COHERENT_RAM_LIMIT #endif ); + enable_mmu_el3(0); } void bl1_plat_arch_setup(void) diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c index 681dc8ad..b6afaa7f 100644 --- a/plat/arm/common/arm_bl2_setup.c +++ b/plat/arm/common/arm_bl2_setup.c @@ -36,16 +36,6 @@ #include <plat_arm.h> #include <string.h> - -/* - * The next 2 constants identify the extents of the code & RO data region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. - */ -#define BL2_RO_BASE (unsigned long)(&__RO_START__) -#define BL2_RO_LIMIT (unsigned long)(&__RO_END__) - #if USE_COHERENT_MEM /* * The next 2 constants identify the extents of the coherent memory region. @@ -234,15 +224,18 @@ void bl2_platform_setup(void) ******************************************************************************/ void arm_bl2_plat_arch_setup(void) { - arm_configure_mmu_el1(bl2_tzram_layout.total_base, + arm_setup_page_tables(bl2_tzram_layout.total_base, bl2_tzram_layout.total_size, - BL2_RO_BASE, - BL2_RO_LIMIT + BL_CODE_BASE, + BL_CODE_LIMIT, + BL_RO_DATA_BASE, + BL_RO_DATA_LIMIT #if USE_COHERENT_MEM , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT #endif ); + enable_mmu_el1(0); } void bl2_plat_arch_setup(void) diff --git a/plat/arm/common/arm_bl2u_setup.c b/plat/arm/common/arm_bl2u_setup.c index 5b7354b3..de7d0c2f 100644 --- a/plat/arm/common/arm_bl2u_setup.c +++ b/plat/arm/common/arm_bl2u_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -36,16 +36,6 @@ #include <plat_arm.h> #include <string.h> - -/* - * The next 2 constants identify the extents of the code & RO data region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. - */ -#define BL2U_RO_BASE (unsigned long)(&__RO_START__) -#define BL2U_RO_LIMIT (unsigned long)(&__RO_END__) - #if USE_COHERENT_MEM /* * The next 2 constants identify the extents of the coherent memory region. @@ -102,16 +92,19 @@ void bl2u_early_platform_setup(meminfo_t *mem_layout, void *plat_info) ******************************************************************************/ void arm_bl2u_plat_arch_setup(void) { - arm_configure_mmu_el1(BL2U_RO_LIMIT, + arm_setup_page_tables(BL2U_BASE, BL31_LIMIT, - BL2U_RO_BASE, - BL2U_RO_LIMIT + BL_CODE_BASE, + BL_CODE_LIMIT, + BL_RO_DATA_BASE, + BL_RO_DATA_LIMIT #if USE_COHERENT_MEM , BL2U_COHERENT_RAM_BASE, BL2U_COHERENT_RAM_LIMIT #endif ); + enable_mmu_el1(0); } void bl2u_plat_arch_setup(void) diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c index 8eb68180..87cafced 100644 --- a/plat/arm/common/arm_bl31_setup.c +++ b/plat/arm/common/arm_bl31_setup.c @@ -38,16 +38,6 @@ #include <plat_arm.h> #include <platform.h> - -/* - * The next 3 constants identify the extents of the code, RO data region and the - * limit of the BL31 image. These addresses are used by the MMU setup code and - * therefore they must be page-aligned. It is the responsibility of the linker - * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols - * refer to page-aligned addresses. - */ -#define BL31_RO_BASE (unsigned long)(&__RO_START__) -#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) #define BL31_END (unsigned long)(&__BL31_END__) #if USE_COHERENT_MEM @@ -246,20 +236,25 @@ void bl31_plat_runtime_setup(void) } /******************************************************************************* - * Perform the very early platform specific architectural setup here. At the - * moment this is only intializes the mmu in a quick and dirty way. + * Perform the very early platform specific architectural setup shared between + * ARM standard platforms. This only does basic initialization. Later + * architectural setup (bl31_arch_setup()) does not do anything platform + * specific. ******************************************************************************/ void arm_bl31_plat_arch_setup(void) { - arm_configure_mmu_el3(BL31_RO_BASE, - (BL31_END - BL31_RO_BASE), - BL31_RO_BASE, - BL31_RO_LIMIT + arm_setup_page_tables(BL31_BASE, + BL31_END - BL31_BASE, + BL_CODE_BASE, + BL_CODE_LIMIT, + BL_RO_DATA_BASE, + BL_RO_DATA_LIMIT #if USE_COHERENT_MEM , BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT #endif ); + enable_mmu_el3(0); } void bl31_plat_arch_setup(void) diff --git a/plat/arm/common/arm_cci.c b/plat/arm/common/arm_cci.c index 41054c24..40cfb480 100644 --- a/plat/arm/common/arm_cci.c +++ b/plat/arm/common/arm_cci.c @@ -32,6 +32,7 @@ #include <cci.h> #include <plat_arm.h> #include <platform_def.h> +#include <utils.h> static const int cci_map[] = { PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX, diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index bcb3f6f6..9e5ddea7 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -85,6 +85,11 @@ $(eval $(call add_define,ARM_BL31_IN_DRAM)) # Enable PSCI_STAT_COUNT/RESIDENCY APIs on ARM platforms ENABLE_PSCI_STAT = 1 +# On ARM platforms, separate the code and read-only data sections to allow +# mapping the former as executable and the latter as execute-never. +SEPARATE_CODE_AND_RODATA := 1 + + PLAT_INCLUDES += -Iinclude/common/tbbr \ -Iinclude/plat/arm/common \ -Iinclude/plat/arm/common/aarch64 diff --git a/plat/arm/common/arm_io_storage.c b/plat/arm/common/arm_io_storage.c index 153fdfe8..42435a74 100644 --- a/plat/arm/common/arm_io_storage.c +++ b/plat/arm/common/arm_io_storage.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -28,7 +28,6 @@ * POSSIBILITY OF SUCH DAMAGE. */ #include <assert.h> -#include <bl_common.h> /* For ARRAY_SIZE */ #include <debug.h> #include <firmware_image_package.h> #include <io_driver.h> @@ -37,6 +36,7 @@ #include <io_storage.h> #include <platform_def.h> #include <string.h> +#include <utils.h> /* IO devices */ static const io_dev_connector_t *fip_dev_con; diff --git a/plat/arm/common/tsp/arm_tsp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c index 2a67fd10..09029f4c 100644 --- a/plat/arm/common/tsp/arm_tsp_setup.c +++ b/plat/arm/common/tsp/arm_tsp_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -35,16 +35,6 @@ #include <platform_tsp.h> #include <plat_arm.h> - -/* - * The next 3 constants identify the extents of the code & RO data region and - * the limit of the BL32 image. These addresses are used by the MMU setup code - * and therefore they must be page-aligned. It is the responsibility of the - * linker script to ensure that __RO_START__, __RO_END__ & & __BL32_END__ - * linker symbols refer to page-aligned addresses. - */ -#define BL32_RO_BASE (unsigned long)(&__RO_START__) -#define BL32_RO_LIMIT (unsigned long)(&__RO_END__) #define BL32_END (unsigned long)(&__BL32_END__) #if USE_COHERENT_MEM @@ -98,13 +88,16 @@ void tsp_platform_setup(void) ******************************************************************************/ void tsp_plat_arch_setup(void) { - arm_configure_mmu_el1(BL32_RO_BASE, - (BL32_END - BL32_RO_BASE), - BL32_RO_BASE, - BL32_RO_LIMIT + arm_setup_page_tables(BL32_BASE, + (BL32_END - BL32_BASE), + BL_CODE_BASE, + BL_CODE_LIMIT, + BL_RO_DATA_BASE, + BL_RO_DATA_LIMIT #if USE_COHERENT_MEM , BL32_COHERENT_RAM_BASE, BL32_COHERENT_RAM_LIMIT #endif ); + enable_mmu_el1(0); } diff --git a/plat/mediatek/mt8173/aarch64/platform_common.c b/plat/mediatek/mt8173/aarch64/platform_common.c index 365df1b0..70639edb 100644 --- a/plat/mediatek/mt8173/aarch64/platform_common.c +++ b/plat/mediatek/mt8173/aarch64/platform_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -34,6 +34,7 @@ #include <debug.h> #include <mt8173_def.h> #include <platform_def.h> +#include <utils.h> #include <xlat_tables.h> static const int cci_map[] = { diff --git a/plat/mediatek/mt8173/plat_mt_gic.c b/plat/mediatek/mt8173/plat_mt_gic.c index c9bdaa90..402a0f4b 100644 --- a/plat/mediatek/mt8173/plat_mt_gic.c +++ b/plat/mediatek/mt8173/plat_mt_gic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -30,6 +30,7 @@ #include <arm_gic.h> #include <bl_common.h> #include <mt8173_def.h> +#include <utils.h> const unsigned int mt_irq_sec_array[] = { MT_IRQ_SEC_SGI_0, diff --git a/plat/rockchip/common/aarch64/platform_common.c b/plat/rockchip/common/aarch64/platform_common.c index 6e9dab79..40cd29e3 100644 --- a/plat/rockchip/common/aarch64/platform_common.c +++ b/plat/rockchip/common/aarch64/platform_common.c @@ -37,6 +37,7 @@ #include <xlat_tables.h> #include <platform_def.h> #include <plat_private.h> +#include <utils.h> #ifdef PLAT_RK_CCI_BASE static const int cci_map[] = { diff --git a/plat/rockchip/common/rockchip_gicv2.c b/plat/rockchip/common/rockchip_gicv2.c index 3e1fa912..c2dca1fc 100644 --- a/plat/rockchip/common/rockchip_gicv2.c +++ b/plat/rockchip/common/rockchip_gicv2.c @@ -31,6 +31,7 @@ #include <bl_common.h> #include <gicv2.h> #include <platform_def.h> +#include <utils.h> /****************************************************************************** * The following functions are defined as weak to allow a platform to override diff --git a/plat/rockchip/common/rockchip_gicv3.c b/plat/rockchip/common/rockchip_gicv3.c index d197aba5..77308965 100644 --- a/plat/rockchip/common/rockchip_gicv3.c +++ b/plat/rockchip/common/rockchip_gicv3.c @@ -32,6 +32,7 @@ #include <gicv3.h> #include <platform.h> #include <platform_def.h> +#include <utils.h> /****************************************************************************** * The following functions are defined as weak to allow a platform to override diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c index 6f1a18b1..ffed591c 100644 --- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c +++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c @@ -147,18 +147,20 @@ void bl31_plat_runtime_setup(void) } /* - * Perform the very early platform specific architectural setup here. At the - * moment this is only intializes the MMU in a quick and dirty way. + * Perform the very early platform specific architectural setup here. */ void bl31_plat_arch_setup(void) { plat_arm_interconnect_init(); plat_arm_interconnect_enter_coherency(); - arm_configure_mmu_el3(BL31_RO_BASE, + arm_setup_page_tables(BL31_RO_BASE, BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE, BL31_RO_BASE, BL31_RO_LIMIT, + 0, + 0, BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT); + enable_mmu_el3(0); } diff --git a/plat/xilinx/zynqmp/pm_service/pm_client.c b/plat/xilinx/zynqmp/pm_service/pm_client.c index d3396dfa..cf0d5f08 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_client.c +++ b/plat/xilinx/zynqmp/pm_service/pm_client.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -37,6 +37,7 @@ #include <gicv2.h> #include <bl_common.h> #include <mmio.h> +#include <utils.h> #include "pm_api_sys.h" #include "pm_client.h" #include "pm_ipi.h" diff --git a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c index 58a3e2a1..ae66fa41 100644 --- a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c +++ b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -90,13 +90,16 @@ void tsp_platform_setup(void) ******************************************************************************/ void tsp_plat_arch_setup(void) { - arm_configure_mmu_el1(BL32_RO_BASE, + arm_setup_page_tables(BL32_RO_BASE, (BL32_END - BL32_RO_BASE), BL32_RO_BASE, - BL32_RO_LIMIT + BL32_RO_LIMIT, + 0, + 0 #if USE_COHERENT_MEM , BL32_COHERENT_RAM_BASE, BL32_COHERENT_RAM_LIMIT #endif ); + enable_mmu_el1(0); } |