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-rw-r--r--plat/common/aarch64/plat_common.c8
-rw-r--r--plat/common/aarch64/platform_helpers.S19
-rw-r--r--plat/common/aarch64/platform_mp_stack.S34
-rw-r--r--plat/common/aarch64/platform_up_stack.S25
-rw-r--r--plat/fvp/aarch64/fvp_common.c2
-rw-r--r--plat/fvp/aarch64/fvp_helpers.S30
-rw-r--r--plat/fvp/bl1_fvp_setup.c2
-rw-r--r--plat/fvp/bl2_fvp_setup.c2
-rw-r--r--plat/fvp/bl31_fvp_setup.c2
-rw-r--r--plat/fvp/bl32_fvp_setup.c2
-rw-r--r--plat/fvp/fvp_def.h7
-rw-r--r--plat/fvp/fvp_pm.c18
-rw-r--r--plat/fvp/include/plat_macros.S78
-rw-r--r--plat/fvp/include/platform_def.h7
-rw-r--r--plat/fvp/platform.mk3
15 files changed, 139 insertions, 100 deletions
diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c
index 94b9dfdf..90574fd6 100644
--- a/plat/common/aarch64/plat_common.c
+++ b/plat/common/aarch64/plat_common.c
@@ -38,12 +38,12 @@
#pragma weak bl31_plat_enable_mmu
#pragma weak bl32_plat_enable_mmu
-void bl31_plat_enable_mmu(void)
+void bl31_plat_enable_mmu(uint32_t flags)
{
- enable_mmu_el3();
+ enable_mmu_el3(flags);
}
-void bl32_plat_enable_mmu(void)
+void bl32_plat_enable_mmu(uint32_t flags)
{
- enable_mmu_el1();
+ enable_mmu_el1(flags);
}
diff --git a/plat/common/aarch64/platform_helpers.S b/plat/common/aarch64/platform_helpers.S
index f6ac13eb..5e2d1b11 100644
--- a/plat/common/aarch64/platform_helpers.S
+++ b/plat/common/aarch64/platform_helpers.S
@@ -37,6 +37,8 @@
.weak platform_is_primary_cpu
.weak platform_check_mpidr
.weak plat_report_exception
+ .weak plat_crash_console_init
+ .weak plat_crash_console_putc
/* -----------------------------------------------------
* int platform_get_core_pos(int mpidr);
@@ -79,3 +81,20 @@ func platform_check_mpidr
*/
func plat_report_exception
ret
+
+ /* -----------------------------------------------------
+ * Placeholder function which should be redefined by
+ * each platform.
+ * -----------------------------------------------------
+ */
+func plat_crash_console_init
+ mov x0, #0
+ ret
+
+ /* -----------------------------------------------------
+ * Placeholder function which should be redefined by
+ * each platform.
+ * -----------------------------------------------------
+ */
+func plat_crash_console_putc
+ ret
diff --git a/plat/common/aarch64/platform_mp_stack.S b/plat/common/aarch64/platform_mp_stack.S
index 801ec7fa..8eb1aa68 100644
--- a/plat/common/aarch64/platform_mp_stack.S
+++ b/plat/common/aarch64/platform_mp_stack.S
@@ -33,29 +33,12 @@
#include <platform_def.h>
- .local pcpu_dv_mem_stack
.local platform_normal_stacks
.weak platform_set_stack
.weak platform_get_stack
- .weak platform_set_coherent_stack
/* -----------------------------------------------------
- * void platform_set_coherent_stack (unsigned long mpidr)
- *
- * For a given CPU, this function sets the stack pointer
- * to a stack allocated in device memory. This stack can
- * be used by C code which enables/disables the SCTLR.M
- * SCTLR.C bit e.g. while powering down a cpu
- * -----------------------------------------------------
- */
-func platform_set_coherent_stack
- mov x5, x30 // lr
- get_mp_stack pcpu_dv_mem_stack, PCPU_DV_MEM_STACK_SIZE
- mov sp, x0
- ret x5
-
- /* -----------------------------------------------------
* unsigned long platform_get_stack (unsigned long mpidr)
*
* For a given CPU, this function returns the stack
@@ -81,22 +64,9 @@ func platform_set_stack
ret x9
/* -----------------------------------------------------
- * Per-cpu stacks in normal memory.
- * Used for C code during runtime execution (when coherent
- * stacks are not required).
- * Each cpu gets a stack of PLATFORM_STACK_SIZE bytes.
+ * Per-cpu stacks in normal memory. Each cpu gets a
+ * stack of PLATFORM_STACK_SIZE bytes.
* -----------------------------------------------------
*/
declare_stack platform_normal_stacks, tzfw_normal_stacks, \
PLATFORM_STACK_SIZE, PLATFORM_CORE_COUNT
-
- /* -----------------------------------------------------
- * Per-cpu stacks in device memory.
- * Used for C code just before power down or right after
- * power up when the MMU or caches need to be turned on
- * or off.
- * Each cpu gets a stack of PCPU_DV_MEM_STACK_SIZE bytes.
- * -----------------------------------------------------
- */
-declare_stack pcpu_dv_mem_stack, tzfw_coherent_mem, \
- PCPU_DV_MEM_STACK_SIZE, PLATFORM_CORE_COUNT
diff --git a/plat/common/aarch64/platform_up_stack.S b/plat/common/aarch64/platform_up_stack.S
index 45a96a64..73b74b2e 100644
--- a/plat/common/aarch64/platform_up_stack.S
+++ b/plat/common/aarch64/platform_up_stack.S
@@ -33,26 +33,9 @@
#include <platform_def.h>
- .local pcpu_dv_mem_stack
.local platform_normal_stacks
.globl platform_set_stack
.globl platform_get_stack
- .globl platform_set_coherent_stack
-
-
- /* -----------------------------------------------------
- * void platform_set_coherent_stack (unsigned long)
- *
- * For cold-boot BL images, only the primary CPU needs a
- * stack. This function sets the stack pointer to a stack
- * allocated in device memory.
- * -----------------------------------------------------
- */
-func platform_set_coherent_stack
- get_up_stack pcpu_dv_mem_stack, PCPU_DV_MEM_STACK_SIZE
- mov sp, x0
- ret
-
/* -----------------------------------------------------
* unsigned long platform_get_stack (unsigned long)
@@ -87,11 +70,3 @@ func platform_set_stack
*/
declare_stack platform_normal_stacks, tzfw_normal_stacks, \
PLATFORM_STACK_SIZE, 1
-
- /* -----------------------------------------------------
- * Single cpu stack in device/coherent memory.
- * PCPU_DV_MEM_STACK_SIZE bytes are allocated.
- * -----------------------------------------------------
- */
-declare_stack pcpu_dv_mem_stack, tzfw_coherent_mem, \
- PCPU_DV_MEM_STACK_SIZE, 1
diff --git a/plat/fvp/aarch64/fvp_common.c b/plat/fvp/aarch64/fvp_common.c
index a10f4e8a..d22fd556 100644
--- a/plat/fvp/aarch64/fvp_common.c
+++ b/plat/fvp/aarch64/fvp_common.c
@@ -119,7 +119,7 @@ const unsigned int num_sec_irqs = sizeof(irq_sec_array) /
mmap_add(fvp_mmap); \
init_xlat_tables(); \
\
- enable_mmu_el##_el(); \
+ enable_mmu_el##_el(0); \
}
/* Define EL1 and EL3 variants of the function initialising the MMU */
diff --git a/plat/fvp/aarch64/fvp_helpers.S b/plat/fvp/aarch64/fvp_helpers.S
index 3cd0b465..823588e4 100644
--- a/plat/fvp/aarch64/fvp_helpers.S
+++ b/plat/fvp/aarch64/fvp_helpers.S
@@ -32,6 +32,7 @@
#include <asm_macros.S>
#include <bl_common.h>
#include <gic_v2.h>
+#include <pl011.h>
#include "../drivers/pwrc/fvp_pwrc.h"
#include "../fvp_def.h"
@@ -39,6 +40,8 @@
.globl plat_secondary_cold_boot_setup
.globl platform_mem_init
.globl plat_report_exception
+ .globl plat_crash_console_init
+ .globl plat_crash_console_putc
.macro fvp_choose_gicmmap param1, param2, x_tmp, w_tmp, res
ldr \x_tmp, =VE_SYSREGS_BASE + V2M_SYS_ID
@@ -187,3 +190,30 @@ func plat_report_exception
add x1, x1, #V2M_SYS_LED
str w0, [x1]
ret
+
+ /* Define a crash console for the plaform */
+#define FVP_CRASH_CONSOLE_BASE PL011_UART0_BASE
+
+ /* ---------------------------------------------
+ * int plat_crash_console_init(void)
+ * Function to initialize the crash console
+ * without a C Runtime to print crash report.
+ * Clobber list : x0, x1, x2
+ * ---------------------------------------------
+ */
+func plat_crash_console_init
+ mov_imm x0, FVP_CRASH_CONSOLE_BASE
+ mov_imm x1, PL011_UART0_CLK_IN_HZ
+ mov_imm x2, PL011_BAUDRATE
+ b console_core_init
+
+ /* ---------------------------------------------
+ * int plat_crash_console_putc(void)
+ * Function to print a character on the crash
+ * console without a C Runtime.
+ * Clobber list : x1, x2
+ * ---------------------------------------------
+ */
+func plat_crash_console_putc
+ mov_imm x1, FVP_CRASH_CONSOLE_BASE
+ b console_core_putc
diff --git a/plat/fvp/bl1_fvp_setup.c b/plat/fvp/bl1_fvp_setup.c
index bfd0f55c..b146fdb7 100644
--- a/plat/fvp/bl1_fvp_setup.c
+++ b/plat/fvp/bl1_fvp_setup.c
@@ -73,7 +73,7 @@ void bl1_early_platform_setup(void)
const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE;
/* Initialize the console to provide early debug support */
- console_init(PL011_UART0_BASE);
+ console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
/* Allow BL1 to see the whole Trusted RAM */
bl1_tzram_layout.total_base = TZRAM_BASE;
diff --git a/plat/fvp/bl2_fvp_setup.c b/plat/fvp/bl2_fvp_setup.c
index beba804e..c0ad3409 100644
--- a/plat/fvp/bl2_fvp_setup.c
+++ b/plat/fvp/bl2_fvp_setup.c
@@ -168,7 +168,7 @@ struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
void bl2_early_platform_setup(meminfo_t *mem_layout)
{
/* Initialize the console to provide early debug support */
- console_init(PL011_UART0_BASE);
+ console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
/* Setup the BL2 memory layout */
bl2_tzram_layout = *mem_layout;
diff --git a/plat/fvp/bl31_fvp_setup.c b/plat/fvp/bl31_fvp_setup.c
index 683097ac..21fca70b 100644
--- a/plat/fvp/bl31_fvp_setup.c
+++ b/plat/fvp/bl31_fvp_setup.c
@@ -145,7 +145,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
void *plat_params_from_bl2)
{
/* Initialize the console to provide early debug support */
- console_init(PL011_UART0_BASE);
+ console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
/* Initialize the platform config for future decision making */
fvp_config_setup();
diff --git a/plat/fvp/bl32_fvp_setup.c b/plat/fvp/bl32_fvp_setup.c
index 901c5857..aa49ff3c 100644
--- a/plat/fvp/bl32_fvp_setup.c
+++ b/plat/fvp/bl32_fvp_setup.c
@@ -72,7 +72,7 @@ void bl32_early_platform_setup(void)
* Initialize a different console than already in use to display
* messages from TSP
*/
- console_init(PL011_UART1_BASE);
+ console_init(PL011_UART1_BASE, PL011_UART1_CLK_IN_HZ, PL011_BAUDRATE);
/* Initialize the platform config for future decision making */
fvp_config_setup();
diff --git a/plat/fvp/fvp_def.h b/plat/fvp/fvp_def.h
index 89c8b023..21edb3be 100644
--- a/plat/fvp/fvp_def.h
+++ b/plat/fvp/fvp_def.h
@@ -198,6 +198,13 @@
#define PL011_UART2_BASE 0x1c0b0000
#define PL011_UART3_BASE 0x1c0c0000
+#define PL011_BAUDRATE 115200
+
+#define PL011_UART0_CLK_IN_HZ 24000000
+#define PL011_UART1_CLK_IN_HZ 24000000
+#define PL011_UART2_CLK_IN_HZ 24000000
+#define PL011_UART3_CLK_IN_HZ 24000000
+
/*******************************************************************************
* TrustZone address space controller related constants
******************************************************************************/
diff --git a/plat/fvp/fvp_pm.c b/plat/fvp/fvp_pm.c
index 55f465ba..22e53e12 100644
--- a/plat/fvp/fvp_pm.c
+++ b/plat/fvp/fvp_pm.c
@@ -120,11 +120,10 @@ exit:
* platform to decide whether the cluster is being turned off and take apt
* actions.
*
- * CAUTION: This function is called with coherent stacks so that caches can be
- * turned off, flushed and coherency disabled. There is no guarantee that caches
- * will remain turned on across calls to this function as each affinity level is
- * dealt with. So do not write & read global variables across calls. It will be
- * wise to do flush a write to the global to prevent unpredictable results.
+ * CAUTION: There is no guarantee that caches will remain turned on across calls
+ * to this function as each affinity level is dealt with. So do not write & read
+ * global variables across calls. It will be wise to do flush a write to the
+ * global to prevent unpredictable results.
******************************************************************************/
int fvp_affinst_off(unsigned long mpidr,
unsigned int afflvl,
@@ -192,11 +191,10 @@ int fvp_affinst_off(unsigned long mpidr,
* platform to decide whether the cluster is being turned off and take apt
* actions.
*
- * CAUTION: This function is called with coherent stacks so that caches can be
- * turned off, flushed and coherency disabled. There is no guarantee that caches
- * will remain turned on across calls to this function as each affinity level is
- * dealt with. So do not write & read global variables across calls. It will be
- * wise to do flush a write to the global to prevent unpredictable results.
+ * CAUTION: There is no guarantee that caches will remain turned on across calls
+ * to this function as each affinity level is dealt with. So do not write & read
+ * global variables across calls. It will be wise to do flush a write to the
+ * global to prevent unpredictable results.
******************************************************************************/
int fvp_affinst_suspend(unsigned long mpidr,
unsigned long sec_entrypoint,
diff --git a/plat/fvp/include/plat_macros.S b/plat/fvp/include/plat_macros.S
index 602eaf1d..727b9580 100644
--- a/plat/fvp/include/plat_macros.S
+++ b/plat/fvp/include/plat_macros.S
@@ -27,31 +27,79 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
-
+#include <cci400.h>
#include <gic_v2.h>
#include <plat_config.h>
+#include "platform_def.h"
.section .rodata.gic_reg_name, "aS"
-gic_regs: .asciz "gic_iar", "gic_ctlr", ""
+gic_regs:
+ .asciz "gic_hppir", "gic_ahppir", "gic_ctlr", ""
+gicd_pend_reg:
+ .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
+newline:
+ .asciz "\n"
+spacer:
+ .asciz ":\t\t0x"
-/* Currently we have only 2 GIC registers to report */
-#define GIC_REG_SIZE (2 * 8)
/* ---------------------------------------------
* The below macro prints out relevant GIC
* registers whenever an unhandled exception is
* taken in BL31.
+ * Clobbers: x0 - x10, x16, sp
* ---------------------------------------------
*/
.macro plat_print_gic_regs
- adr x0, plat_config;
- ldr w0, [x0, #CONFIG_GICC_BASE_OFFSET]
- /* gic base address is now in x0 */
- ldr w1, [x0, #GICC_IAR]
- ldr w2, [x0, #GICC_CTLR]
- sub sp, sp, #GIC_REG_SIZE
- stp x1, x2, [sp] /* we store the gic registers as 64 bit */
- adr x0, gic_regs
- mov x1, sp
- bl print_string_value
- add sp, sp, #GIC_REG_SIZE
+ adr x0, plat_config
+ ldr w16, [x0, #CONFIG_GICC_BASE_OFFSET]
+ cbz x16, 1f
+ /* gic base address is now in x16 */
+ adr x6, gic_regs /* Load the gic reg list to x6 */
+ /* Load the gic regs to gp regs used by str_in_crash_buf_print */
+ ldr w8, [x16, #GICC_HPPIR]
+ ldr w9, [x16, #GICC_AHPPIR]
+ ldr w10, [x16, #GICC_CTLR]
+ /* Store to the crash buf and print to cosole */
+ bl str_in_crash_buf_print
+
+ /* Print the GICD_ISPENDR regs */
+ add x7, x16, #GICD_ISPENDR
+ adr x4, gicd_pend_reg
+ bl asm_print_str
+2:
+ sub x4, x7, x16
+ cmp x4, #0x280
+ b.eq 1f
+ bl asm_print_hex
+ adr x4, spacer
+ bl asm_print_str
+ ldr x4, [x7], #8
+ bl asm_print_hex
+ adr x4, newline
+ bl asm_print_str
+ b 2b
+1:
+ .endm
+
+.section .rodata.cci_reg_name, "aS"
+cci_iface_regs:
+ .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
+
+ /* ------------------------------------------------
+ * The below macro prints out relevant interconnect
+ * registers whenever an unhandled exception is
+ * taken in BL31.
+ * Clobbers: x0 - x9, sp
+ * ------------------------------------------------
+ */
+ .macro plat_print_interconnect_regs
+ adr x6, cci_iface_regs
+ /* Store in x7 the base address of the first interface */
+ mov_imm x7, (CCI400_BASE + SLAVE_IFACE3_OFFSET)
+ ldr w8, [x7, #SNOOP_CTRL_REG]
+ /* Store in x7 the base address of the second interface */
+ mov_imm x7, (CCI400_BASE + SLAVE_IFACE4_OFFSET)
+ ldr w9, [x7, #SNOOP_CTRL_REG]
+ /* Store to the crash buf and print to console */
+ bl str_in_crash_buf_print
.endm
diff --git a/plat/fvp/include/platform_def.h b/plat/fvp/include/platform_def.h
index ec4cf525..99832663 100644
--- a/plat/fvp/include/platform_def.h
+++ b/plat/fvp/include/platform_def.h
@@ -47,13 +47,6 @@
/* Size of cacheable stacks */
#define PLATFORM_STACK_SIZE 0x800
-/* Size of coherent stacks for debug and release builds */
-#if DEBUG
-#define PCPU_DV_MEM_STACK_SIZE 0x400
-#else
-#define PCPU_DV_MEM_STACK_SIZE 0x300
-#endif
-
#define FIRMWARE_WELCOME_STR "Booting trusted firmware boot loader stage 1\n\r"
/* Trusted Boot Firmware BL2 */
diff --git a/plat/fvp/platform.mk b/plat/fvp/platform.mk
index b22a3393..f6275b78 100644
--- a/plat/fvp/platform.mk
+++ b/plat/fvp/platform.mk
@@ -45,8 +45,7 @@ $(eval $(call add_define,TSP_RAM_LOCATION_ID))
PLAT_INCLUDES := -Iplat/fvp/include/
-PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011.c \
- drivers/arm/pl011/pl011_console.c \
+PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \
drivers/io/io_fip.c \
drivers/io/io_memmap.c \
drivers/io/io_semihosting.c \
generated by cgit (git 2.34.1) at 2025-07-16 19:48:37 +0000