diff options
Diffstat (limited to 'services/std_svc/psci/psci_common.c')
| -rw-r--r-- | services/std_svc/psci/psci_common.c | 40 |
1 files changed, 15 insertions, 25 deletions
diff --git a/services/std_svc/psci/psci_common.c b/services/std_svc/psci/psci_common.c index 0a1cdf9e..d8c8618f 100644 --- a/services/std_svc/psci/psci_common.c +++ b/services/std_svc/psci/psci_common.c @@ -290,15 +290,14 @@ int psci_validate_mpidr(unsigned long mpidr, int level) /******************************************************************************* * This function determines the full entrypoint information for the requested - * PSCI entrypoint on power on/resume and saves this in the non-secure CPU - * cpu_context, ready for when the core boots. + * PSCI entrypoint on power on/resume and returns it. ******************************************************************************/ -int psci_save_ns_entry(uint64_t mpidr, - uint64_t entrypoint, uint64_t context_id, - uint32_t ns_scr_el3, uint32_t ns_sctlr_el1) +int psci_get_ns_ep_info(entry_point_info_t *ep, + uint64_t entrypoint, uint64_t context_id) { uint32_t ep_attr, mode, sctlr, daif, ee; - entry_point_info_t ep; + uint32_t ns_scr_el3 = read_scr_el3(); + uint32_t ns_sctlr_el1 = read_sctlr_el1(); sctlr = ns_scr_el3 & SCR_HCE_BIT ? read_sctlr_el2() : ns_sctlr_el1; ee = 0; @@ -308,11 +307,11 @@ int psci_save_ns_entry(uint64_t mpidr, ep_attr |= EP_EE_BIG; ee = 1; } - SET_PARAM_HEAD(&ep, PARAM_EP, VERSION_1, ep_attr); + SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr); - ep.pc = entrypoint; - memset(&ep.args, 0, sizeof(ep.args)); - ep.args.arg0 = context_id; + ep->pc = entrypoint; + memset(&ep->args, 0, sizeof(ep->args)); + ep->args.arg0 = context_id; /* * Figure out whether the cpu enters the non-secure address space @@ -329,7 +328,7 @@ int psci_save_ns_entry(uint64_t mpidr, mode = ns_scr_el3 & SCR_HCE_BIT ? MODE_EL2 : MODE_EL1; - ep.spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + ep->spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); } else { mode = ns_scr_el3 & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc; @@ -340,12 +339,9 @@ int psci_save_ns_entry(uint64_t mpidr, */ daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT; - ep.spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, daif); + ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, daif); } - /* initialise an entrypoint to set up the CPU context */ - cm_init_context(mpidr, &ep); - return PSCI_E_SUCCESS; } @@ -442,12 +438,12 @@ unsigned short psci_get_phys_state(aff_map_node_t *node) * topology tree and calls the physical power on handler for the corresponding * affinity levels ******************************************************************************/ -static int psci_call_power_on_handlers(aff_map_node_t *mpidr_nodes[], +static void psci_call_power_on_handlers(aff_map_node_t *mpidr_nodes[], int start_afflvl, int end_afflvl, afflvl_power_on_finisher_t *pon_handlers) { - int rc = PSCI_E_INVALID_PARAMS, level; + int level; aff_map_node_t *node; for (level = end_afflvl; level >= start_afflvl; level--) { @@ -461,12 +457,8 @@ static int psci_call_power_on_handlers(aff_map_node_t *mpidr_nodes[], * so simply return an error and let the caller take * care of the situation. */ - rc = pon_handlers[level](node); - if (rc != PSCI_E_SUCCESS) - break; + pon_handlers[level](node); } - - return rc; } /******************************************************************************* @@ -528,12 +520,10 @@ void psci_afflvl_power_on_finish(int start_afflvl, psci_set_max_phys_off_afflvl(max_phys_off_afflvl); /* Perform generic, architecture and platform specific handling */ - rc = psci_call_power_on_handlers(mpidr_nodes, + psci_call_power_on_handlers(mpidr_nodes, start_afflvl, end_afflvl, pon_handlers); - if (rc != PSCI_E_SUCCESS) - panic(); /* * This function updates the state of each affinity instance |