From 3cf300e7695e6883787ce01d5c4b97ced96bb8c1 Mon Sep 17 00:00:00 2001 From: Igal Liberman Date: Thu, 18 May 2017 18:38:58 +0300 Subject: fix: pcie: temporarily disable pcie clock fix After commit "f82b49e fix: pcie: cp110: fix pcie clock selection" we encountered some instabilities in PCIe. This patch disables the PCIe clock fix temporarily, until we figure out the root cause for this this issue. Change-Id: I521e4495118fab2bcbe1e99e6080d1cbb2b08f39 Signed-off-by: Igal Liberman Reviewed-on: http://vgitil04.il.marvell.com:8080/39663 Tested-by: iSoC Platform CI Reviewed-by: Kostya Porotchkin Reviewed-on: http://vgitil04.il.marvell.com:8080/39759 --- drivers/marvell/mochi/cp110_setup.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/marvell/mochi/cp110_setup.c b/drivers/marvell/mochi/cp110_setup.c index 579dc9f7..fcbd16ae 100644 --- a/drivers/marvell/mochi/cp110_setup.c +++ b/drivers/marvell/mochi/cp110_setup.c @@ -310,6 +310,12 @@ void cp110_pcie_clk_cfg(int cp_index) mmio_write_32(MVEBU_PCIE_REF_CLK_BUF_CTRL(cp_index), reg); } +#if 0 + /* + * TODO: Some instabilities in PCIe occur after introducing this code. + * Until we understand the root cause of this issue, + * disable it temporarily. + */ /* CP110 revision A1 */ if (cp110_rev_id_get() == MVEBU_CP110_REF_ID_A1) { if (!pcie0_clk || !pcie1_clk) { @@ -323,6 +329,7 @@ void cp110_pcie_clk_cfg(int cp_index) mmio_write_32(MVEBU_CP_MSS_DPSHSR_REG(cp_index), reg); } } +#endif } /* Set a unique stream id for all DMA capable devices */ -- cgit