From b78a69eceb32db72ea66f0e349f6480883dab68c Mon Sep 17 00:00:00 2001 From: Terry Zhou Date: Mon, 19 Mar 2018 18:23:39 +0200 Subject: a3900: add a3900_z2 platform support A3900_z2 platform use AP807 & CP110 Change-Id: Ida7200cc4aa8846e9666a1288952ecb6c93d25b4 Signed-off-by: Terry Zhou Reviewed-on: http://vgitil04.il.marvell.com:8080/52171 Reviewed-by: Kostya Porotchkin Tested-by: iSoC Platform CI --- plat/marvell/a8k/a3900_z2/board/dram_port.c | 72 ++++++++++++ .../a8k/a3900_z2/board/marvell_plat_config.c | 121 +++++++++++++++++++++ plat/marvell/a8k/a3900_z2/plat_def.h | 16 +++ plat/marvell/a8k/a3900_z2/platform.mk | 17 +++ 4 files changed, 226 insertions(+) create mode 100644 plat/marvell/a8k/a3900_z2/board/dram_port.c create mode 100644 plat/marvell/a8k/a3900_z2/board/marvell_plat_config.c create mode 100644 plat/marvell/a8k/a3900_z2/plat_def.h create mode 100644 plat/marvell/a8k/a3900_z2/platform.mk diff --git a/plat/marvell/a8k/a3900_z2/board/dram_port.c b/plat/marvell/a8k/a3900_z2/board/dram_port.c new file mode 100644 index 00000000..2aead3c4 --- /dev/null +++ b/plat/marvell/a8k/a3900_z2/board/dram_port.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#include +#include +#include +#include + +/* + * This function may modify the default DRAM parameters + * based on information recieved from SPD or bootloader + * configuration located on non volatile storage + */ +void plat_dram_update_topology(void) +{ + NOTICE("Gathering DRAM information\n"); +} + +/* + * This struct provides the DRAM training code with + * the appropriate board DRAM configuration + */ +struct mv_ddr_iface dram_iface_ap0 = { + .ap_base = MVEBU_REGS_BASE_AP(0), + .state = MV_DDR_IFACE_NRDY, + .id = 0, + .iface_base_addr = 0, + .tm = { + /* FIXME: Z0 board 1CS 8Gb x16 devices of micron - 2400P */ + DEBUG_LEVEL_ERROR, + 0x1, /* active interfaces */ + /* cs_mask, mirror, dqs_swap, ck_swap X subphys */ + { { { {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0} }, + SPEED_BIN_DDR_2400R, /* speed_bin */ + MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */ + MV_DDR_DIE_CAP_8GBIT, /* die capacity */ + MV_DDR_FREQ_SAR, /* frequency */ + 0, 0, /* cas_l, cas_wl */ + MV_DDR_TEMP_LOW} }, /* temperature */ + BUS_MASK_32BIT, /* subphys mask */ + MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ + { {0} }, /* raw spd data */ + {0} /* timing parameters */ + }, +}; + +/* Pointer to the first DRAM interface in the system */ +struct mv_ddr_iface *ptr_iface = &dram_iface_ap0; + +struct mv_ddr_iface *mv_ddr_iface_get(void) +{ + /* Return current ddr interface */ + return ptr_iface; +} + +struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) +{ + /* Return the board topology as defined in the board code */ + return &ptr_iface->tm; +} diff --git a/plat/marvell/a8k/a3900_z2/board/marvell_plat_config.c b/plat/marvell/a8k/a3900_z2/board/marvell_plat_config.c new file mode 100644 index 00000000..7c35f755 --- /dev/null +++ b/plat/marvell/a8k/a3900_z2/board/marvell_plat_config.c @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#include +/* + * If bootrom is currently at BLE there's no need to include the memory + * maps structure at this point + */ +#include +#ifndef IMAGE_BLE + +/******************************************************************************* + * AMB Configuration + ******************************************************************************/ +struct addr_map_win *amb_memory_map; + +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +{ + *win = amb_memory_map; + if (*win == NULL) + *size = 0; + else + *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + + return 0; +} +#endif + +/******************************************************************************* + * IO WIN Configuration + ******************************************************************************/ +struct addr_map_win io_win_memory_map[] = { +#ifndef IMAGE_BLE + /* SB (MCi0) internal regs */ + {0x00000000f9000000, 0x800000, MCI_0_TID}, + /* SB (MCi1) internal regs */ + {0x00000000f9800000, 0x800000, MCI_1_TID}, + /* MCI 0 indirect window */ + {MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID}, + /* MCI 1 indirect window */ + {MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID}, +#endif +}; + +uint32_t marvell_get_io_win_gcr_target(int ap_index) +{ + return PIDI_TID; +} + +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +{ + *win = io_win_memory_map; + if (*win == NULL) + *size = 0; + else + *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + + return 0; +} + +#ifndef IMAGE_BLE +/******************************************************************************* + * IOB Configuration + ******************************************************************************/ +struct addr_map_win iob_memory_map[] = { + /* PEX2_X1 window */ + {0x00000000f8000000, 0x1000000, PEX2_TID}, + /* PEX0_X4 window */ + {0x00000000f6000000, 0x1000000, PEX0_TID}, + {0x00000000c0000000, 0x30000000, PEX0_TID}, +}; + +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +{ + *win = iob_memory_map; + *size = sizeof(iob_memory_map)/sizeof(iob_memory_map[0]); + + return 0; +} +#endif + +/******************************************************************************* + * CCU Configuration + ******************************************************************************/ +struct addr_map_win ccu_memory_map[] = { /* IO window */ +#ifdef IMAGE_BLE + {0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */ +#else + {0x00000000f2000000, 0xe000000, IO_0_TID}, + {0x00000000c0000000, 0x30000000, IO_0_TID}, +#endif +}; + +uint32_t marvell_get_ccu_gcr_target(int ap) +{ + return DRAM_0_TID; +} + +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +{ + *win = ccu_memory_map; + *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + + return 0; +} + +#ifdef IMAGE_BLE +/******************************************************************************* + * SKIP IMAGE Configuration + ******************************************************************************/ + +void *plat_get_skip_image_data(void) +{ + /* No recovery button on A3900 VD/AXIS/BT boards */ + return NULL; +} +#endif diff --git a/plat/marvell/a8k/a3900_z2/plat_def.h b/plat/marvell/a8k/a3900_z2/plat_def.h new file mode 100644 index 00000000..d7d62410 --- /dev/null +++ b/plat/marvell/a8k/a3900_z2/plat_def.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef __MVEBU_DEF_H__ +#define __MVEBU_DEF_H__ + +#include + +/* A3900 has single CP0 */ +#define CP_COUNT 1 + +#endif /* __MVEBU_DEF_H__ */ diff --git a/plat/marvell/a8k/a3900_z2/platform.mk b/plat/marvell/a8k/a3900_z2/platform.mk new file mode 100644 index 00000000..64923a5f --- /dev/null +++ b/plat/marvell/a8k/a3900_z2/platform.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2018 Marvell International Ltd. +# +# SPDX-License-Identifier: BSD-3-Clause +# https://spdx.org/licenses +# + +include plat/marvell/a8k/common/a8k_common.mk + +include plat/marvell/common/marvell_common.mk + +# A3900 Z2 use AP807 instead AP806, update the source list +BL31_SOURCES := $(filter-out $(MARVELL_DRV_BASE)/mochi/apn806_setup.c, $(BL31_SOURCES)) +BL31_SOURCES += $(MARVELL_DRV_BASE)/mochi/ap807_setup.c + +BLE_SOURCES := $(filter-out $(MARVELL_DRV_BASE)/mochi/apn806_setup.c, $(BLE_SOURCES)) +BLE_SOURCES += $(MARVELL_DRV_BASE)/mochi/ap807_setup.c \ No newline at end of file -- cgit