From 3738274dc1b40ad846d41d7bfd6a597bcfba9e70 Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Mon, 18 Nov 2013 17:26:59 +0000 Subject: Unmask SError and Debug exceptions. Any asynchronous exception caused by the firmware should be handled in the firmware itself. For this reason, unmask SError exceptions (and Debug ones as well) on all boot paths. Also route external abort and SError interrupts to EL3, otherwise they will target EL1. Change-Id: I9c191d2d0dcfef85f265641c8460dfbb4d112092 --- common/psci/psci_afflvl_suspend.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'common/psci/psci_afflvl_suspend.c') diff --git a/common/psci/psci_afflvl_suspend.c b/common/psci/psci_afflvl_suspend.c index 030f15dd..9a2c0cfb 100644 --- a/common/psci/psci_afflvl_suspend.c +++ b/common/psci/psci_afflvl_suspend.c @@ -82,6 +82,8 @@ static int psci_afflvl0_suspend(unsigned long mpidr, psci_secure_context[index].tcr = read_tcr(); psci_secure_context[index].ttbr = read_ttbr0(); psci_secure_context[index].vbar = read_vbar(); + psci_secure_context[index].pstate = + read_daif() & (DAIF_ABT_BIT | DAIF_DBG_BIT); /* Set the secure world (EL3) re-entry point after BL1 */ psci_entrypoint = (unsigned long) psci_aff_suspend_finish_entry; @@ -370,6 +372,7 @@ static unsigned int psci_afflvl0_suspend_finish(unsigned long mpidr, * context in the right order. */ write_vbar(psci_secure_context[index].vbar); + write_daif(read_daif() | psci_secure_context[index].pstate); write_mair(psci_secure_context[index].mair); write_tcr(psci_secure_context[index].tcr); write_ttbr0(psci_secure_context[index].ttbr); -- cgit