From 74eb26e4098d0a1f5c6ef49c1355e99d80027f36 Mon Sep 17 00:00:00 2001 From: Juan Castillo Date: Wed, 13 Jan 2016 15:01:09 +0000 Subject: ARM platforms: rationalise memory attributes of shared memory The shared memory region on ARM platforms contains the mailboxes and, on Juno, the payload area for communication with the SCP. This shared memory may be configured as normal memory or device memory at build time by setting the platform flag 'PLAT_ARM_SHARED_RAM_CACHED' (on Juno, the value of this flag is defined by 'MHU_PAYLOAD_CACHED'). When set as normal memory, the platform port performs the corresponding cache maintenance operations. From a functional point of view, this is the equivalent of setting the shared memory as device memory, so there is no need to maintain both options. This patch removes the option to specify the shared memory as normal memory on ARM platforms. Shared memory is always treated as device memory. Cache maintenance operations are no longer needed and have been replaced by data memory barriers to guarantee that payload and MHU are accessed in the right order. Change-Id: I7f958621d6a536dd4f0fa8768385eedc4295e79f --- include/plat/arm/css/common/css_def.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'include/plat/arm/css/common/css_def.h') diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h index c900278b..7a5d1939 100644 --- a/include/plat/arm/css/common/css_def.h +++ b/include/plat/arm/css/common/css_def.h @@ -37,8 +37,6 @@ /************************************************************************* * Definitions common to all ARM Compute SubSystems (CSS) *************************************************************************/ -#define MHU_PAYLOAD_CACHED 0 - #define NSROM_BASE 0x1f000000 #define NSROM_SIZE 0x00001000 @@ -118,8 +116,6 @@ #define SCP_BL2U_BASE BL31_BASE -#define PLAT_ARM_SHARED_RAM_CACHED MHU_PAYLOAD_CACHED - /* Load address of Non-Secure Image for CSS platform ports */ #define PLAT_ARM_NS_IMAGE_OFFSET 0xE0000000 -- cgit