From d3f70af6e09d669da9c7d7890b7af5a0cdc4b3a5 Mon Sep 17 00:00:00 2001 From: Soby Mathew Date: Thu, 14 Aug 2014 13:36:41 +0100 Subject: Add CPU specific crash reporting handlers This patch adds handlers for dumping Cortex-A57 and Cortex-A53 specific register state to the CPU specific operations framework. The contents of CPUECTLR_EL1 are dumped currently. Change-Id: I63d3dbfc4ac52fef5e25a8cf6b937c6f0975c8ab --- lib/cpus/aarch64/aem_generic.S | 13 +++++++++++++ lib/cpus/aarch64/cortex_a53.S | 18 ++++++++++++++++++ lib/cpus/aarch64/cortex_a57.S | 19 +++++++++++++++++++ lib/cpus/aarch64/cpu_helpers.S | 24 ++++++++++++++++++++++++ 4 files changed, 74 insertions(+) (limited to 'lib/cpus') diff --git a/lib/cpus/aarch64/aem_generic.S b/lib/cpus/aarch64/aem_generic.S index 19c94336..58a64a6c 100644 --- a/lib/cpus/aarch64/aem_generic.S +++ b/lib/cpus/aarch64/aem_generic.S @@ -68,6 +68,19 @@ func aem_generic_cluster_pwr_dwn mov x0, #DCCISW b dcsw_op_all + /* --------------------------------------------- + * This function provides cpu specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +func aem_generic_cpu_reg_dump + mov x6, #0 /* no registers to report */ + ret + /* cpu_ops for Base AEM FVP */ declare_cpu_ops aem_generic, BASE_AEM_MIDR, 1 diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S index 08cc9381..722ce7af 100644 --- a/lib/cpus/aarch64/cortex_a53.S +++ b/lib/cpus/aarch64/cortex_a53.S @@ -119,4 +119,22 @@ func cortex_a53_cluster_pwr_dwn mov x30, x18 b cortex_a53_disable_smp + /* --------------------------------------------- + * This function provides cortex_a53 specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_a53_regs, "aS" +cortex_a53_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_a53_cpu_reg_dump + adr x6, cortex_a53_regs + mrs x8, CPUECTLR_EL1 + ret + declare_cpu_ops cortex_a53, CORTEX_A53_MIDR diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index 8de7fe92..8b788566 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -167,4 +167,23 @@ func cortex_a57_cluster_pwr_dwn mov x30, x18 b cortex_a57_disable_ext_debug + /* --------------------------------------------- + * This function provides cortex_a57 specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_a57_regs, "aS" +cortex_a57_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_a57_cpu_reg_dump + adr x6, cortex_a57_regs + mrs x8, CPUECTLR_EL1 + ret + + declare_cpu_ops cortex_a57, CORTEX_A57_MIDR diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S index 624a4597..46584b3f 100644 --- a/lib/cpus/aarch64/cpu_helpers.S +++ b/lib/cpus/aarch64/cpu_helpers.S @@ -125,6 +125,30 @@ func init_cpu_ops ret #endif /* IMAGE_BL31 */ +#if IMAGE_BL31 && CRASH_REPORTING + /* + * The cpu specific registers which need to be reported in a crash + * are reported via cpu_ops cpu_reg_dump function. After a matching + * cpu_ops structure entry is found, the correponding cpu_reg_dump + * in the cpu_ops is invoked. + */ + .globl do_cpu_reg_dump +func do_cpu_reg_dump + mov x16, x30 + + /* Get the matching cpu_ops pointer */ + bl get_cpu_ops_ptr + cbz x0, 1f + + /* Get the cpu_ops cpu_reg_dump */ + ldr x2, [x0, #CPU_REG_DUMP] + cbz x2, 1f + blr x2 +1: + mov x30, x16 + ret +#endif + /* * The below function returns the cpu_ops structure matching the * midr of the core. It reads the MIDR_EL1 and finds the matching -- cgit