From 2f5dcfef1db42f3b073ae657f8a94925abecd768 Mon Sep 17 00:00:00 2001 From: Andrew Thoelke Date: Mon, 28 Apr 2014 12:06:18 +0100 Subject: Replace disable_mmu with assembler version disable_mmu() cannot work as a C function as there is no control over data accesses generated by the compiler between disabling and cleaning the data cache. This results in reading stale data from main memory. As assembler version is provided for EL3, and a variant that also disables the instruction cache which is now used by the BL1 exception handling function. Fixes ARM-software/tf-issues#147 Change-Id: I0cf394d2579a125a23c2f2989c2e92ace6ddb1a6 --- lib/aarch64/misc_helpers.S | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'lib') diff --git a/lib/aarch64/misc_helpers.S b/lib/aarch64/misc_helpers.S index c33ade28..bccc936a 100644 --- a/lib/aarch64/misc_helpers.S +++ b/lib/aarch64/misc_helpers.S @@ -79,6 +79,9 @@ .globl zeromem16 .globl memcpy16 + .globl disable_mmu_el3 + .globl disable_mmu_icache_el3 + func get_afflvl_shift cmp x0, #3 @@ -332,3 +335,27 @@ m_loop1: subs x2, x2, #1 b.ne m_loop1 m_end: ret + +/* --------------------------------------------------------------------------- + * Disable the MMU at EL3 + * This is implemented in assembler to ensure that the data cache is cleaned + * and invalidated after the MMU is disabled without any intervening cacheable + * data accesses + * --------------------------------------------------------------------------- + */ + +func disable_mmu_el3 + mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT) +do_disable_mmu: + mrs x0, sctlr_el3 + bic x0, x0, x1 + msr sctlr_el3, x0 + isb // ensure MMU is off + mov x0, #DCCISW // DCache clean and invalidate + b dcsw_op_all + + +func disable_mmu_icache_el3 + mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT) + b do_disable_mmu + -- cgit