From 5541bb3f61ae97b49203939f940931455b2f3037 Mon Sep 17 00:00:00 2001 From: Soby Mathew Date: Mon, 22 Sep 2014 14:13:34 +0100 Subject: Optimize Cortex-A57 cluster power down sequence on Juno This patch optimizes the Cortex-A57 cluster power down sequence by not flushing the Level1 data cache. The L1 data cache and the L2 unified cache are inclusive. A flush of the L2 by set/way flushes any dirty lines from the L1 as well. This is a known safe deviation from the Cortex-A57 TRM defined power down sequence. This optimization can be enabled by the platform through the 'SKIP_A57_L1_FLUSH_PWR_DWN' build flag. Each Cortex-A57 based platform must make its own decision on whether to use the optimization. This patch also renames the cpu-errata-workarounds.md to cpu-specific-build-macros.md as this facilitates documentation of both CPU Specific errata and CPU Specific Optimization build macros. Change-Id: I299b9fe79e9a7e08e8a0dffb7d345f9a00a71480 --- lib/cpus/aarch64/cortex_a57.S | 3 ++- lib/cpus/cpu-errata.mk | 48 ------------------------------------ lib/cpus/cpu-ops.mk | 57 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 59 insertions(+), 49 deletions(-) delete mode 100644 lib/cpus/cpu-errata.mk create mode 100644 lib/cpus/cpu-ops.mk (limited to 'lib') diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index c2e11bd9..dab16d7e 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -222,13 +222,14 @@ func cortex_a57_cluster_pwr_dwn */ bl cortex_a57_disable_l2_prefetch +#if !SKIP_A57_L1_FLUSH_PWR_DWN /* ------------------------------------------------- * Flush the L1 caches. * ------------------------------------------------- */ mov x0, #DCCISW bl dcsw_op_level1 - +#endif /* --------------------------------------------- * Disable the optional ACP. * --------------------------------------------- diff --git a/lib/cpus/cpu-errata.mk b/lib/cpus/cpu-errata.mk deleted file mode 100644 index 79f0156d..00000000 --- a/lib/cpus/cpu-errata.mk +++ /dev/null @@ -1,48 +0,0 @@ -# -# Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# Neither the name of ARM nor the names of its contributors may be used -# to endorse or promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -# CPU Errata Build flags. These should be enabled by the -# platform if the errata needs to be applied. - -# Flag to apply errata 806969 during reset. This errata applies only to -# revision r0p0 of the Cortex A57 cpu. -ERRATA_A57_806969 ?=0 - -# Flag to apply errata 813420 during reset. This errata applies only to -# revision r0p0 of the Cortex A57 cpu. -ERRATA_A57_813420 ?=0 - -# Process ERRATA_A57_806969 flag -$(eval $(call assert_boolean,ERRATA_A57_806969)) -$(eval $(call add_define,ERRATA_A57_806969)) - -# Process ERRATA_A57_813420 flag -$(eval $(call assert_boolean,ERRATA_A57_813420)) -$(eval $(call add_define,ERRATA_A57_813420)) diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk new file mode 100644 index 00000000..1c5512e9 --- /dev/null +++ b/lib/cpus/cpu-ops.mk @@ -0,0 +1,57 @@ +# +# Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# Cortex A57 specific optimisation to skip L1 cache flush when +# cluster is powered down. +SKIP_A57_L1_FLUSH_PWR_DWN ?=0 + +# Process SKIP_A57_L1_FLUSH_PWR_DWN flag +$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN)) +$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN)) + + +# CPU Errata Build flags. These should be enabled by the +# platform if the errata needs to be applied. + +# Flag to apply errata 806969 during reset. This errata applies only to +# revision r0p0 of the Cortex A57 cpu. +ERRATA_A57_806969 ?=0 + +# Flag to apply errata 813420 during reset. This errata applies only to +# revision r0p0 of the Cortex A57 cpu. +ERRATA_A57_813420 ?=0 + +# Process ERRATA_A57_806969 flag +$(eval $(call assert_boolean,ERRATA_A57_806969)) +$(eval $(call add_define,ERRATA_A57_806969)) + +# Process ERRATA_A57_813420 flag +$(eval $(call assert_boolean,ERRATA_A57_813420)) +$(eval $(call add_define,ERRATA_A57_813420)) -- cgit