From 167a935733a6e3e412b8ed6a60034d0d84895f2e Mon Sep 17 00:00:00 2001 From: Andrew Thoelke Date: Wed, 4 Jun 2014 21:10:52 +0100 Subject: Initialise CPU contexts from entry_point_info Consolidate all BL3-1 CPU context initialization for cold boot, PSCI and SPDs into two functions: * The first uses entry_point_info to initialize the relevant cpu_context for first entry into a lower exception level on a CPU * The second populates the EL1 and EL2 system registers as needed from the cpu_context to ensure correct entry into the lower EL This patch alters the way that BL3-1 determines which exception level is used when first entering EL1 or EL2 during cold boot - this is now fully determined by the SPSR value in the entry_point_info for BL3-3, as set up by the platform code in BL2 (or otherwise provided to BL3-1). In the situation that EL1 (or svc mode) is selected for a processor that supports EL2, the context management code will now configure all essential EL2 register state to ensure correct execution of EL1. This allows the platform code to run non-secure EL1 payloads directly without requiring a small EL2 stub or OS loader. Change-Id: If9fbb2417e82d2226e47568203d5a369f39d3b0f --- services/std_svc/psci/psci_setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'services/std_svc/psci/psci_setup.c') diff --git a/services/std_svc/psci/psci_setup.c b/services/std_svc/psci/psci_setup.c index 015beabb..af821506 100644 --- a/services/std_svc/psci/psci_setup.c +++ b/services/std_svc/psci/psci_setup.c @@ -59,7 +59,7 @@ static aff_limits_node_t psci_aff_limits[MPIDR_MAX_AFFLVL + 1]; /******************************************************************************* * 'psci_ns_einfo_idx' keeps track of the next free index in the - * 'psci_ns_entry_info' & 'psci_suspend_context' arrays. + * 'psci_suspend_context' arrays. ******************************************************************************/ static unsigned int psci_ns_einfo_idx; -- cgit