diff options
author | Russell King <rmk+kernel@armlinux.org.uk> | 2020-06-03 15:34:01 +0100 |
---|---|---|
committer | Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2025-04-04 15:00:01 +0100 |
commit | 68f43258624169b23e45dd8065f53b1021b31acb (patch) | |
tree | 1bf6eef3bdf5d394ac7e1eca17c9bdcbf4e367bf | |
parent | 38fec10eb60d687e30c8c6b5420d86e8149f7557 (diff) |
PCI: mobiveil: fix 5.7 merge errors
Fix errors in the mobiveil version that was merged in 5.7 kernels:
- the type of "root_bus_nr" was changed from "u8" to "char", but
it is compared to values that are typed as "unsigned char".
Depending whether a platform has "char" as signed or unsigned,
this may not do what is intended.
- ls_g4_pcie_reinit_hw() now returns a success/failure value, and
follows the Linux style of return 0 on success and -ve errno on
failure. However, the testing in ls_pcie_g4_reset() expects 0
on failure, so we won't call ls_ig4_pcie_enable_interrupt() except
if ls_g4_pcie_reinit_hw() has failed - which is likely not what
was intended.
Fixes: d29ad70a813b ("PCI: mobiveil: Add PCIe Gen4 RC driver for Layerscape SoCs")
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
-rw-r--r-- | drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c index 5af22bee913b..79b9d17318cf 100644 --- a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c +++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c @@ -53,6 +53,17 @@ static inline void ls_g4_pcie_pf_writel(struct ls_g4_pcie *pcie, iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); } +static bool ls_g4_pcie_is_bridge(struct ls_g4_pcie *pcie) +{ + struct mobiveil_pcie *mv_pci = &pcie->pci; + u32 header_type; + + header_type = mobiveil_csr_readb(mv_pci, PCI_HEADER_TYPE); + header_type &= 0x7f; + + return header_type == PCI_HEADER_TYPE_BRIDGE; +} + static int ls_g4_pcie_link_up(struct mobiveil_pcie *pci) { struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci); @@ -184,7 +195,7 @@ static void ls_g4_pcie_reset(struct work_struct *work) ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; mobiveil_csr_writew(mv_pci, ctrl, PCI_BRIDGE_CONTROL); - if (!ls_g4_pcie_reinit_hw(pcie)) + if (ls_g4_pcie_reinit_hw(pcie)) return; ls_g4_pcie_enable_interrupt(pcie); @@ -234,6 +245,9 @@ static int __init ls_g4_pcie_probe(struct platform_device *pdev) return ret; } + if (!ls_g4_pcie_is_bridge(pcie)) + return -ENODEV; + ls_g4_pcie_enable_interrupt(pcie); return 0; |