diff options
| author | Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2023-05-27 21:09:07 +0100 |
|---|---|---|
| committer | Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2025-04-04 14:59:18 +0100 |
| commit | 1d39a0b4e340595662565f5fc64f6baccc0188e1 (patch) | |
| tree | 6ce234ef21cfc87028836a45c1626bec0b74565d | |
| parent | d1c6c073ef9a88552d97b47a2ca719ba0e77d449 (diff) | |
arm64: dts: add SolidRun CN9130 SOM dtsi
Add the dts include file for the SolidRun CN9130 SOM (which is designed
to be attached to another board to make a functional system.) This SOM
is designed to be inter-changeable with the Armada 388 SOM used on
SolidRun's Clearfog Base and Pro platforms.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
| -rw-r--r-- | arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi b/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi index cb8d54895a77..ea3339b80b96 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi @@ -59,6 +59,7 @@ }; }; +/* EMMC */ &ap_sdhci0 { bus-width = <8>; pinctrl-0 = <&ap_mmc0_pins>; @@ -80,12 +81,14 @@ status = "okay"; }; +/* For Assy=PHY_ETH */ &cp0_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&cp0_i2c0_pins>; clock-frequency = <100000>; status = "okay"; + /* M24C02-WMN6TP / ST24C02WP */ som_eeprom: eeprom@53 { compatible = "atmel,24c02"; reg = <0x53>; @@ -97,8 +100,9 @@ pinctrl-0 = <&cp0_mdio_pins>; status = "okay"; - /* assembly option */ + /* For Assy=PHY_ETH */ cp0_eth2_phy: ethernet-phy@0 { + marvell,reg-init = <3 16 0 0x0064>; reg = <0>; }; }; @@ -130,7 +134,7 @@ marvell,function = "ge1"; }; - cp0_i2c0_pins: cp0-i2c0-pins { + cp0_i2c0_pins: cp0-i2c-pins-0 { marvell,pins = "mpp37", "mpp38"; marvell,function = "i2c0"; }; @@ -140,7 +144,7 @@ marvell,function = "ge"; }; - cp0_spi1_pins: cp0-spi1-pins { + cp0_spi1_pins: cp0-spi-pins-1 { marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; marvell,function = "spi1"; }; |