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| author | Jon Lin <jon.lin@rock-chips.com> | 2022-02-16 09:40:26 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2022-02-17 17:15:08 +0000 |
| commit | 3a4bf922d42efa4e9a3dc803d1fd786d43e8a501 (patch) | |
| tree | 41f2f81a72d4757cdd6e339a93a06a9f9d759c9b /scripts/gdb/linux/proc.py | |
| parent | 869f2c94db92f0f1d6acd0dff1c1ebb8160f5e29 (diff) | |
spi: rockchip: Preset cs-high and clk polarity in setup progress
After power up, the cs and clock is in default status, and the cs-high
and clock polarity dts property configuration will take no effect until
the calling of rockchip_spi_config in the first transmission.
So preset them to make sure a correct voltage before the first
transmission coming.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Link: https://lore.kernel.org/r/20220216014028.8123-5-jon.lin@rock-chips.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/proc.py')
0 files changed, 0 insertions, 0 deletions