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Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Keep the clearfog DTS file ordered alphabetically - Florian placed the
MDIO entry after pinctrl, which mis-orders the file.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add SFP module support for Clearfog using the SFP phylink support.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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All the devices on I2C0 support fast mode, so increase the bus speed
to match. The Armada 388 is known to have a timing issue when in
standard mode, which we believe causes the ficticious device at 0x64
to appear.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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As we now support 1000BaseX and 2500BaseX phy interface modes, we can
select the appropriate autoneg mode and advertising masks from the
phy interface mode.
We also need to set the phy interface mode when different SFP modules
are plugged in (causing changes in the autonegotiation mode.)
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Attach the phy to the net device so that the generic phy calls can
access the attached phy without having to use phylink veneers.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Switch to relying on the rtnetlink lock rather than our private config
mutex to ensure proper locking.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Hold the rtnetlink lock while causing phylink to prevent changes to
the networking configuration. This will allow us to eliminate the
configuration locking in phylink, and thus simplify the locking
strategy.
This will also allow phylink to attach the phy directly to the net
device, so allowing a reduction in veneer code.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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When the MAC reports a link failure, it can be momentary. Ensure
that the event is reported by latching the loss of link, so that the
worker reports link down.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Some 10Gigabit PHYs automatically switch the mode of their host
interface depending on their negotiated speed. We need to communicate
this to the MAC driver so the MAC can switch its host interface to
match the PHYs new operating mode. Provide the current PHY interface
mode to the MAC driver.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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The Marvell driver incorrectly provides phydev->lp_advertising as the
logical and of the link partner's advert and our advert. This is
incorrect - this field is supposed to store the link parter's unmodified
advertisment.
This allows ethtool to report the correct link partner auto-negotiation
status.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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The Marvell PHYs support pause frame advertisments, so we should not be
masking their support off. Add the necessary flag to the Marvell PHY
to allow any MAC level pause frame support to be advertised.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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The Marvell PHYs support pause frame advertisments, so we should not be
masking their support off. Add the necessary flag to the Marvell PHY
to allow any MAC level pause frame support to be advertised.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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The Marvell PHYs support pause frame advertisments, so we should not be
masking their support off. Add the necessary flag to the Marvell PHY
to allow any MAC level pause frame support to be advertised.
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add support for reading module EEPROMs through phylink.
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add EEE support to mvneta. This allows us to enable the low power idle
support at MAC level if there is a PHY attached through phylink which
supports LPI. The appropriate ethtool support is provided to allow the
feature to be controlled, including ethtool statistics for EEE wakeup
errors.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add EEE hooks to phylink to allow the phylib EEE functions for the
connected phy to be safely accessed.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Allow symetric flow control to be enabled for fixed link connections as
well as other types of connections by setting the supported and
advertised capability bits.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Enable flow control support for PHY connections by indicating our
support via the ethtool capabilities. phylink takes care of the
appropriate handling.
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add flow control support to mvneta, including the ethtool hooks. This
uses the phylink code to calculate the result of autonegotiation where
a phy is attached, and to handle the ethtool settings.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add flow control support, including ethtool support, to phylink. We
add support to allow ethtool to get and set the current flow control
settings, and the 802.3 specified resolution for the local and remote
link partner abilities.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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mvneta is the only user of fixed_phy_update_state(), which has been
converted to use phylink instead. Remove fixed_phy_update_state().
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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The PSC sync change interrupt can fire multiple times while the link is
down. As this isn't information we make use of, it's pointless having
the interrupt enabled, so let's disable this interrupt.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Convert mvneta to use phylink, which models the MAC to PHY link in
a generic, reusable form.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
- remove unused sync status
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Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add support for SFP hotpluggable modules via phylink. This supports
both copper and optical SFP modules, which require different Serdes
modes in order to properly negotiate the link.
Optical SFP modules typically require the Serdes link to be talking
1000base-X mode - this is the gigabit ethernet mode defined by the
802.3 standard.
Copper SFP modules typically integrate a PHY in the module to convert
from Serdes to copper, and the PHY will be configured by the vendor
to either present a 1000base-X Serdes link (for fixed 1000base-T) or
a SGMII Serdes link. However, this is vendor defined, so we instead
detect the PHY, switch the link to SGMII mode, and use traditional
PHY based negotiation.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
- set port and port capability depending on connector type
- move autoneg mode setting to probe function
- set "supported" speed capabilities depending on reported ethernet
capabilities
- checks for short read
- dump eeprom base ID when checksum fails
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Add wake-on-lan support to phylink.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add ethtool nway_reset support to phylink, to allow userspace to
request a re-negotiation of the link.
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add support for reading and writing the clause 45 MII registers.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add support to phylink for SFP, which needs to control and configure
the ethernet MAC link state. Specifically, SFP needs to:
1. set the negotiation mode between SGMII and 1000base-X
2. attach and detach the module PHY
3. prevent the link coming up when errors are reported
In the absence of a PHY, we also need to set the ethtool port type
according to the module plugged in.
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
- rework phylink_set_link_*(), combining into a single function.
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The link between the ethernet MAC and its PHY has become more complex
as the interface evolves. This is especially true with serdes links,
where the part of the PHY is effectively integrated into the MAC.
Serdes links can be connected to a variety of devices, including SFF
modules soldered down onto the board with the MAC, a SFP cage with
a hotpluggable SFP module which may contain a PHY or directly modulate
the serdes signals onto optical media with or without a PHY, or even
a classical PHY connection.
Moreover, the negotiation information on serdes links comes in two
varieties - SGMII mode, where the PHY provides its speed/duplex/flow
control information to the MAC, and 1000base-X mode where both ends
exchange their abilities and each resolve the link capabilities.
This means we need a more flexible means to support these arrangements,
particularly with the hotpluggable nature of SFP, where the PHY can
be attached or detached after the network device has been brought up.
Ethtool information can come from multiple sources:
- we may have a PHY operating in either SGMII or 1000base-X mode, in
which case we take ethtool/mii data directly from the PHY.
- we may have a optical SFP module without a PHY, with the MAC
operating in 1000base-X mode - the ethtool/mii data needs to come
from the MAC.
- we may have a copper SFP module with a PHY whic can't be accessed,
which means we need to take ethtool/mii data from the MAC.
Phylink aims to solve this by providing an intermediary between the
MAC and PHY, providing a safe way for PHYs to be hotplugged, and
allowing a SFP driver to reconfigure the serdes connection.
Phylink also takes over support of fixed link connections, where the
speed/duplex/flow control are fixed, but link status may be controlled
by a GPIO signal. By avoiding the fixed-phy implementation, phylink
can provide a faster response to link events: fixed-phy has to wait for
phylib to operate its state machine, which can take several seconds.
In comparison, phylink takes milliseconds.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
- remove sync status
- rework supported and advertisment handling
- add 1000base-x speed for fixed links
- use functionality exported from phy-core, reworking
__phylink_ethtool_ksettings_set for it
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Add an I2C MDIO bus bridge library, to allow phylib to access PHYs which
are connected to an I2C bus instead of the more conventional MDIO bus.
Such PHYs can be found in SFP adapters and SFF modules.
Since PHYs appear at I2C bus address 0x40..0x5f, and 0x50/0x51 are
reserved for SFP EEPROMs/diagnostics, we must not allow the MDIO bus
to access these I2C addresses.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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phylink will need phy_start_machine exported, so lets export it as a
GPL symbol. Documentation/networking/phy.txt indicates that this
should be a PHY API function.
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Sometimes, we need to do additional work between the PHY coming up and
marking the carrier present - for example, we may need to wait for the
PHY to MAC link to finish negotiation. This changes phylib to provide
a notification function pointer which avoids the built-in
netif_carrier_on() and netif_carrier_off() functions.
Standard ->adjust_link functionality is provided by hooking a helper
into the new ->phy_link_change method.
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add the missing 1000Base-X entry to the phy settings table. This was
not included because the original code could not cope with more than
32 bits of link mode mask.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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phy-core
phy_lookup_setting() provides useful functionality in ethtool code
outside phylib. Move it to phy-core and allow it to be re-used (eg,
in phylink) rather than duplicated elsewhere. Note that this supports
the larger linkmode space.
As we move the phy settings table, we also need to move the guts of
phy_supported_speeds() as well.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Other code would like to make use of this, so make the speed and duplex
string generation visible, and place it in a separate file.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Allow the phy settings table to support more than 32 link modes by
switching to the ethtool link mode bit number representation, rather
than storing the mask. This will allow phylink and other ethtool
code to share the settings table to look up settings.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Add phylib support for the Marvell Alaska X 10 Gigabit PHY (MV88X3310).
This phy is able to operate at 10G, 1G, 100M and 10M speeds, and only
supports Clause 45 accesses.
The PHY appears (based on the vendor IDs) to be two different vendors
IP, with each devad containing several instances.
This PHY driver has only been tested with the RJ45 copper port and a
Marvell Armada 8040-based ethernet interface.
It should be noted that to use the full range of speeds, MAC drivers
need to also reconfigure the link mode as per phydev->interface, since
the PHY automatically changes its interface mode depending on the
negotiated speed.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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XAUI allows XGMII to reach an extended distance by using a XGXS layer at
each end of the MAC to PHY link, operating over four Serdes lanes.
10GBASE-KR is a single lane Serdes backplane ethernet connection method
with autonegotiation on the link. Some PHYs use this to connect to the
ethernet interface at 10G speeds, switching to other connection types
when utilising slower speeds.
10GBASE-KR is also used for XFI and SFI to connect to XFP and SFP fiber
modules.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Move the old 10G genphy support to sit beside the new clause 45 library
functions, so all the 10G phy code is together.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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