summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2014-05-12ARM: i.MX27 pca100: remove deprecated IRQF_DISABLEDJuan Solano
This flag is a NOOP and can be removed now. Signed-off-by: Juan Solano <jsm@jsolano.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-05-12ARM: imx/mxs defconfigs: add MTD_SPI_NOR (new dependency for M25P80)Brian Norris
These defconfigs contain the CONFIG_M25P80 symbol, which is now dependent on the MTD_SPI_NOR symbol. Add CONFIG_MTD_SPI_NOR to satisfy the new dependency. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-05-12ARM: i.MX: Fix eMMa PrP resource sizeAlexander Shiyan
Last address for eMMa PrP is 0x80...0x83, so increase resource size for eMMa to 256. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-05-12ARM: imx_v4_v5_defconfig: drop CONFIG_COMMON_CLK_DEBUG optionShawn Guo
The option COMMON_CLK_DEBUG was removed by commit ea72dc2 (clk: remove CONFIG_COMMON_CLK_DEBUG), so let's remove CONFIG_COMMON_CLK_DEBUG from the defconfig. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-05-12ARM: i.MX27 clk: Remove clk_register_clkdev() for unused clocksAlexander Shiyan
This patch removes clk_register_clkdev() for the clocks that do not have any users for non-DT boards and drivers. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-05-12ARM: i.MX27 clk: Add missing clocks for MSHC and RTICAlexander Shiyan
This patch adds missing clocks handling for the Memory Stick Host Controller (MSHC) and Run-Time Integrity Checker (RTIC). Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-05-12ARM: imx6q: add the missing esai_ahb clockShawn Guo
The esai_ahb clock is derived from ahb and used to provide ESAI the capability of register accessing and FSYS clock source for I2S clocks dividing. The gate bits of this esai_ahb clock are shared with the esai clock -- the baud clock, so we need to call imx_clk_gate2_shared() for these two clocks. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-05-12ARM: imx: add shared gate clock supportShawn Guo
It's quite common on i.MX that one gate bit controls the gating of multiple clocks, i.e. this is a shared gate. The patch adds the function imx_clk_gate2_shared() for such case. The clocks controlled by the same gate bits should call this function with a pointer to a single share count variable, so that the gate bits will only be operated on the first enabling and the last disabling of these shared gate clocks. Thanks to Gerhard Sittig <gsi@denx.de> for this idea. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-05-12ARM: imx: lock is always valid for clk_gate2Shawn Guo
The imx specific clk_gate2 always has a valid lock with the clock. So the validation on gate->lock is not really needed. Remove it. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-05-12ARM: imx: define struct clk_gate2 on our ownShawn Guo
The imx clk-gate2 driver implements an i.MX specific gate clock, which has two bits controlling the gate states. While this is a completely separate gate driver from the common clk-gate one, it reuses the common clk_gate structure. Such reusing makes the extending of clk_gate2 clumsy. Let's define struct clk_gate2 on our own to make the driver independent of the common clk-gate one, and ease the clk_gate2 extending at a later time. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-05-12ARM: i.MX: Remove #ifdef CONFIG_OFAlexander Shiyan
CONFIG_OF is always selected for i.MX. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-05-12ARM: imx_v6_v7_defconfig: enable option CONFIG_LOCALVERSION_AUTOShawn Guo
Option CONFIG_LOCALVERSION_AUTO is quite helpful to tell kernel version. I do not see any reason why we should unset it. Let's remove the unset to have it enabled. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-05-12ARM: imx: drop CONFIG_MMC_UNSAFE_RESUME from defconfigShawn Guo
Since 2501c91 (mmc: core: Use MMC_UNSAFE_RESUME as default behavior), CONFIG_MMC_UNSAFE_RESUME is not available anymore. Drop it from imx defconfig. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-05-12ARM: imx6: clk: i.MX6 DualLite/Solo i2c4 clockIain Paton
Compared to i.MX6 Quad/Dual the CCM_CCGR1 register in the i.MX6 Solo/DualLite replaces the ecspi5 clock with the i2c4 clock. Handle this difference using cpu_is_imx6dl(). Signed-off-by: Iain Paton <ipaton0@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-05-12ARM: imx_v6_v7_defconfig: enable cpufreq and CMA supportShawn Guo
- Enable imx6 cpufreq support with ondemand governor - Enable CMA support so that device like 1080p HDMI can work - Run savedefconfig Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-05-12ARM: shmobile: Remove unused r8a7791_init_early()Magnus Damm
Remove the now unused r8a7791_init_early() function. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2014-05-12ARM: shmobile: Use r8a7791 DT CPU Frequency for KoelschMagnus Damm
Convert the Koelsch board support to use shmobile_init_delay() to be able to migrate away from per-SoC delay setup functions. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2014-05-12ARM: shmobile: Use r8a7791 DT CPU Frequency in common caseMagnus Damm
Convert the common C-code-less r8a7791 DT board support to use shmobile_init_delay() to be able to migrate away from per-SoC delay setup functions. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2014-05-11ARM: shmobile: Remove unused r8a7740_init_delay()Magnus Damm
Remove the now unused r8a7740_init_delay() function. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Tested-by: Geert Uytterhoeven <geert@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2014-05-11ARM: shmobile: Use r8a7740 DT CPU Frequency for Armadillo DT RefMagnus Damm
Convert the Armadillo r8a7740 DT reference board support to use shmobile_init_delay() to be able to migrate away from per-SoC delay setup functions. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Tested-by: Geert Uytterhoeven <geert@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2014-05-11ARM: shmobile: Use r8a7740 DT CPU Frequency in common caseMagnus Damm
Convert the common C-code-less r8a7740 DT board support to use shmobile_init_delay() to be able to migrate away from per-SoC delay setup functions. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Tested-by: Geert Uytterhoeven <geert@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2014-05-11ARM: shmobile: Add r8a7740 Maximum CPU Frequency to DTSMagnus Damm
Add 800 MHz to the r8a7740 DTS to describe the maximum CPU frequency. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Tested-by: Geert Uytterhoeven <geert@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2014-05-11ARM: shmobile: r8a7740: Correct name of DT Ethernet clockGeert Uytterhoeven
The preferred node name in DT for an Ethernet device is "ethernet". "sh-eth" was used in preliminary and incomplete bindings. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2014-05-08ARM: mvebu: Fix pmsu compilation when ARMv6 is selectedVincent Stehlé
When compiling for multiplatform for both ARMv6 and ARMv7, the default compiler flags are for ARMv6, and we will get: /tmp/ccwDEzd0.s: Assembler messages: /tmp/ccwDEzd0.s:639: Error: selected processor does not support ARM mode `isb ' /tmp/ccwDEzd0.s:645: Error: selected processor does not support ARM mode `isb ' /tmp/ccwDEzd0.s:646: Error: selected processor does not support ARM mode `dsb ' /tmp/ccwDEzd0.s:695: Error: selected processor does not support ARM mode `isb ' make[1]: *** [arch/arm/mach-mvebu/pmsu.o] Error 1 Fix this in a similar manner than done previously in commit 72533b77d30c2be02672e26b5dde1263d7b4c2be, by specifying ARMv7 flags for pmsu.o. Signed-off-by: Vincent Stehlé <vincent.stehle@laposte.net> Link: https://lkml.kernel.org/r/1399407782-29091-1-git-send-email-vincent.stehle@laposte.net Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Gregory Clement <gregory.clement@free-electrons.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: conditionalize Armada 375 coherency workaroundThomas Petazzoni
The Armada 375 coherency workaround only needs to be applied to the Z1 revision of the SoC. The A0 and later revisions have been fixed, and no longer need this workaround. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1399302326-6917-6-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: conditionalize Armada 375 SMP workaroundThomas Petazzoni
The Armada 375 SMP workaround only needs to be applied to the Z1 revision of the SoC. The A0 and later revisions have been fixed, and no longer need this workaround. Note that the initialization of the SMP workaround is delayed from ->smp_prepare_cpus() to ->smp_boot_secondary() because when ->smp_prepare_cpus() is called, the early initcalls have not be called, so the mvebu-soc-id mechanism is not operational. Since the workaround is anyway not needed before the secondary CPU is started, we can delay its implementation until the ->smp_boot_secondary() call. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1399302326-6917-5-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: add Armada 375 A0 revision definitionThomas Petazzoni
Now that we have access to Armada 375 A0 platforms, we can add the corresponding revision definition in mvebu-soc-id.h. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1399302326-6917-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: initialize mvebu-soc-id earlierThomas Petazzoni
Currently, the mvebu-soc-id logic is initialized through a core_initcall(). However, we will soon need to know the SoC revision before booting secondary CPUs, because a workaround affects Armada 375 Z1 steppings, but should not be applied on Armada 375 A0 steppings. Unfortunately, core_initcall() are called way too late compared to the SMP initialization. Therefore, the mvebu-soc-id initialization is move to an early_initcall(), which is called before the SMP initialization. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1399302326-6917-3-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: fix thermal quirk SoC revision checkThomas Petazzoni
In commit 54fe26a900bc528f3df1e4235cb6b9ca5c6d4dc2 ('ARM: mvebu: Add thermal quirk for the Armada 375 DB board'), a check on the Armada SoC revision was added to decide whether a quirk for the thermal device should be applied or not. However, the quirk implementation has a bug: it assumes mvebu_get_soc_id() returns true on success, but it returns 0. Therefore, the condition: if (mvebu_get_soc_id(&dev, &rev) && rev > ARMADA_375_Z1_REV) is always false (as long as mvebu-soc-id is properly initialized). As a consequence, the quirk is always applied, even on A0 steppings, for which the quirk should not be applied. This was spotted by testing the thermal driver on Armada 375 A0, which Ezequiel could not do since he does not have access to the A0 revision of the SoC for the moment. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1399302326-6917-2-git-send-email-thomas.petazzoni@free-electrons.com Fixes: 54fe26a900bc528f3df1e4235cb6b9ca5c6d4dc2 ('ARM: mvebu: Add thermal quirk for the Armada 375 DB board') Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: Kirkwood: t5325: Remove platform device to instantiate audioAndrew Lunn
Remove platform device instantiating of the audio, which results in board-t5325.c being removed. A DT node will be added to take its place. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1399141819-23924-7-git-send-email-andrew@lunn.ch Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: Kirkwood: Remove platform driver for codecAndrew Lunn
Remove the platform driver and platform data for the audio codec. A DT node will replace it. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1399141819-23924-3-git-send-email-andrew@lunn.ch Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: Add thermal quirk for the Armada 375 DB boardEzequiel Garcia
The initial release of the Armada 375 DB board has an Armada 375 Z1 stepping silicon. This commit introduces a quirk that allows to workaround a series of issues with the thermal sensor in this stepping, but updating the devicetree: * Updates the compatible string for the thermal, so the driver can perform a specific initialization of the sensor. * Moves the offset of the thermal control register. This quirk allows to specifiy the correct (A0 stepping) offset in the devicetree. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1398371004-15807-9-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: Select HAVE_ARM_TWD only if SMP is enabledEzequiel Garcia
HAVE_ARM_TWD depends on SMP, so we should only select it if SMP is enabled, as the others platforms do. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1398339276-5754-1-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: fix the name of the parameter used in mvebu_get_soc_idGregory CLEMENT
The name of the two parameters of mvebu_get_soc_id were inverted. This patch fix it in order to have a more readable code. Reported-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397925170-8202-3-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: remove unnecessary ifdef around l2x0_of_initGregory CLEMENT
l2x0_of_init function is always defined arch/arm/include/asm/hardware/cache-l2x0.h: in case of CONFIG_CACHE_L2X0 is not selected then a placeholder is defined. Then there is no need to have ifdef around l2x0_of_init. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397925170-8202-2-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: register the cpuidle driver for the Armada XP SoCsGregory CLEMENT
The cpuidle is a platform driver so we register the device just after the initialization of the board in an arch_initcall. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397488214-20685-12-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08cpuidle: mvebu: Add initial CPU idle support for Armada 370/XP SoCGregory CLEMENT
Add the wfi, cpu idle and cpu deep idle power states support for the Armada XP SoCs. All the latencies and the power consumption values used at the "armada_370_xp_idle_driver" structure are preliminary and will be modified in the future after running some measurements and analysis. Based on the work of Nadav Haklai. Signed-off-by: Nadav Haklai <nadavh@marvell.com> Link: https://lkml.kernel.org/r/1397488214-20685-11-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397488214-20685-11-git-send-email-gregory.clement@free-electrons.com Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: Register notifier callback for the cpuidle transitionGregory CLEMENT
In order to have well encapsulated code, we use notifier callbacks for CPU_PM_ENTER and CPU_PM_EXIT inside the mvebu power management code. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397488214-20685-10-git-send-email-gregory.clement@free-electrons.com Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: refine which files are build in mach-mvebuThomas Petazzoni
Following the integration into mach-mvebu of the Kirkwood ARMv5 support, we need to be more careful about which files get built. For example, the pmsu.c file now calls wfi(), which only exists on ARMv7 platforms. Therefore, this commit changes mach-mvebu/Makefile to build the Armada 370/XP/375/38x specific files only when CONFIG_MACH_MVEBU_V7 is enabled. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1398709239-6126-1-git-send-email-thomas.petazzoni@free-electrons.com Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: Add the PMSU related part of the cpu idle functionsGregory CLEMENT
The cpu idle support will need to access to Power Management Service Unit. This commit adds the architecture related functions that will be used in the idle path of the cpuidle driver. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397488214-20685-9-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: Allow to power down L2 cache controller in idle modeGregory CLEMENT
This commit adds a function which adjusts the PMSU configuration to automatically power down the L2 and coherency fabric when we enter a certain idle state. This feature is part of the Power Management Service Unit of the Armada 370 and Armada XP SoCs. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397488214-20685-8-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: Low level function to disable HW coherency supportGregory CLEMENT
When going to deep idle we need to disable the SoC snooping (aka hardware coherency support). Playing with the coherency fabric requires to use assembly code to be sure that the compiler doesn't reorder the instructions nor do wrong optimization. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397488214-20685-7-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: Split low level functions to manipulate HW coherencyGregory CLEMENT
Actually enabling coherency and adding a CPU on a SMP group are two different operations which can be done separately. This patch splits this in two functions. Moreover as they use common pattern, this patch also creates local low level functions (ll_get_coherency_base and ll_get_cpuid) to be used by the exposed functions (ll_add_cpu_to_smp_group and ll_enable_coherency) Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397488214-20685-6-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: Remove the unused argument of set_cpu_coherent()Gregory CLEMENT
set_cpu_coherent() took the SMP group ID as parameter. But this parameter was never used, and the CPU always uses the SMP group 0. So we can remove this parameter. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397488214-20685-5-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: ll_set_cpu_coherent always uses the current CPUGregory CLEMENT
ll_set_cpu_coherent is always used on the current CPU, so instead of passing the CPU id as argument, ll_set_cpu_coherent() can find it by itself. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397488214-20685-4-git-send-email-gregory.clement@free-electrons.com Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: remove the address parameter for ll_set_cpu_coherentGregory CLEMENT
In order to be able to deal with the MMU enabled and the MMU disabled cases, the base address of the coherency registers was passed to the function. The address by itself was not interesting as it can't change for a given SoC, the only thing we need is to have a distinction between the physical or the virtual address. This patch add a check of the MMU bit to choose the accurate address, then the calling function doesn't have to pass this information. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397488214-20685-3-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: add Armada 38x compatible string to pmsuThomas Petazzoni
Since the Armada 38x PMSU registers are slightly different than the Armada 370/XP PMSU ones, we introduce a new compatible string "armada-380-pmsu" in the PMSU driver. These differences are not visible for the current usage of the PMSU, but they might become visible in the future. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397483648-26611-8-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: add workaround for SMP support for Armada 375 stepping Z1Gregory CLEMENT
Due to internal bootrom issue, CPU[1] initial jump code (four instructions) should be placed in SRAM memory of the SoC. In order to achieve this, we have to unmap the BootROM and at some specific location where the BootROM was place, create a specific MBus window for the SRAM. This SRAM is initialized with a few instructions of code that allows to jump into the real secondary CPU boot address. This workaround will most likely be disabled when newer steppings of the Armada 375 will be made available, in which case a dynamic test based on mvebu-soc-id will be added. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397483648-26611-10-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397483648-26611-10-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: add SMP support for Armada 375 and Armada 38xGregory CLEMENT
This commit adds the SMP support for Armada 375 and Armada 38x. It turns out that the SMP logic for both of these SOCs are fairly similar, the only differences being: * A different method to set the secondary CPU boot address * An Armada 375 specific workaround needed for the early Z1 stepping, added by the following patch. Other than that, the patch is fairly straightforward and adds the usual platsmp and headsmp code, defining the smp_operations structure that is referenced from the DT_MACHINE structures. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397483648-26611-9-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397483648-26611-9-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08ARM: mvebu: add function to set the resume boot address for Armada 375Gregory CLEMENT
In order to boot the secondary CPUs on Armada 375, we need to set the boot address of these CPUs, through a register part of the System Controller (this deviates from the Armada XP design, where the boot address was defined using a register part of the PMSU unit). Therefore, this commit adds a new helper function in the System Controller driver to set the secondary CPU boot address. Moreover, it moves the System Controller initialization as an early_initcall(), since arch_initcall() is too late for an SMP-related initialization. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397483648-26611-7-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397483648-26611-7-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
generated by cgit (git 2.34.1) at 2025-07-15 20:39:09 +0000