summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2023-03-21drm: Add SDP Error Detection Configuration RegisterArun R Murthy
DP2.0 E11 defines a new register to facilitate SDP error detection by a 128B/132B capable DPRX device. v2: Update the macro name to reflect the DP spec(Harry) Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/20230302081532.765821-2-arun.r.murthy@intel.com
2023-03-21drm/i915/bios: Rename find_section to find_bdb_sectionMaarten Lankhorst
This prevents a namespace collision on other archs. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230315121924.2314693-1-jani.nikula@intel.com
2023-03-21drm/i915/debugfs: add crtc i915_pipe debugfs fileJani Nikula
The pipe may differ from crtc index if pipes are fused off. For testing purposes, IGT needs to know the pipe. There's already a I915_GET_PIPE_FROM_CRTC_ID IOCTL for this. However, the upcoming Xe driver won't have that IOCTL, and going forward, we'll want a unified interface for testing i915 and Xe, as they share the display code. Thus add the debugfs for i915 display. v2: User letters for pipe names (Ville) Cc: Bhanuprakash Modem <bhanuprakash.modem@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230320124429.786985-2-jani.nikula@intel.com
2023-03-21drm/i915/debugfs: switch crtc debugfs to struct intel_crtcJani Nikula
Convert the crtc debugfs code to use struct intel_crtc instead of struct drm_crtc. v2: Fix build for CONFIG_DRM_I915_DEBUG_VBLANK_EVADE=y (kernel test robot) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230320124429.786985-1-jani.nikula@intel.com
2023-03-20drm/i915/audio: update audio keepalive clock valuesClint Taylor
BSPEC has updated the cdclk audio keepalives AUD_TS_CDCLK_M value to 60 for all supported platforms and refclks. BSPEC: 54034 BSPEC: 55409 BSPEC: 65243 Cc: Kai Vehmanen <kai.vehmanen@linux.intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230316234654.3797572-1-clinton.a.taylor@intel.com
2023-03-20drm/i915/psr: clean up PSR debugfs sink status error handlingJani Nikula
Handle errors first and return early, and reduce indentation on the happy day code path. Cc: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230317134144.223936-3-jani.nikula@intel.com
2023-03-20drm/i915/psr: switch PSR debugfs to struct intel_connectorJani Nikula
Prefer struct intel_connector over struct drm_connector. Cc: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230317134144.223936-2-jani.nikula@intel.com
2023-03-20drm/i915/psr: move PSR debugfs to intel_psr.cJani Nikula
Move the debugfs next to the implementation. Cc: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230317134144.223936-1-jani.nikula@intel.com
2023-03-18drm/i915: Extract intel_crtc_scanline_offset()Ville Syrjälä
Pull the scanline_offset calculation into its own function. Might have further use for this later with DSB scanline waits. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230310235828.17439-4-ville.syrjala@linux.intel.com
2023-03-18drm/i915: Relocate intel_crtc_update_active_timings()Ville Syrjälä
Move intel_crtc_update_active_timings() into intel_vblank.c where it more properly belongs. Also do the s/dev_priv/i915/ modernization rename while at it. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230310235828.17439-3-ville.syrjala@linux.intel.com
2023-03-18drm/i915: Add belts and suspenders locking for seamless M/N changesVille Syrjälä
Add some (probably overkill) locking to protect the vblank timestamping constants updates during seamless M/N fastsets. As everything should be naturally aligned I think the individual pieces should probably end up updating atomically enough. So this is only really meant to guarantee everyone sees a consistent whole. All the drm_vblank.c usage is covered by vblank_time_lock, and uncore.lock will take care of __intel_get_crtc_scanline() that can also be called from outside the core vblank functionality. Currently only crtc_clock and framedur_ns can change, but in the future might fastset also across eg. vtotal/vblank_end changes, so let's just grab the locks across the whole thing. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230310235828.17439-2-ville.syrjala@linux.intel.com
2023-03-18drm/i915: Update vblank timestamping stuff on seamless M/N changeVille Syrjälä
When we change the M/N values seamlessly during a fastset we should also update the vblank timestamping stuff to make sure the vblank timestamp corrections/guesstimations come out exact. Note that only crtc_clock and framedur_ns can actually end up changing here during fastsets. Everything else we touch can only change during full modesets. Technically we should try to do this exactly at the start of vblank, but that would require some kind of double buffering scheme. Let's skip that for now and just update things right after the commit has been submitted to the hardware. This means the information will be properly up to date when the vblank irq handler goes to work. Only if someone ends up querying some vblanky stuff in between the commit and start of vblank may we see a slight discrepancy. Also this same problem really exists for the DRRS downclocking stuff. But as that is supposed to be more or less transparent to the user, and it only drops to low gear after a long delay (1 sec currently) we probably don't have to worry about it. Any time something is actively submitting updates DRRS will remain in high gear and so the timestamping constants will match the hardware state. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Fixes: e6f29923c048 ("drm/i915: Allow M/N change during fastset on bdw+") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230310235828.17439-1-ville.syrjala@linux.intel.com
2023-03-17drm/i915: Extract intel_sprite_uapi.cVille Syrjälä
Move the sprite colorkey ioctl handler to its own file so that intel_sprite.c becomes all about the low level details of pre-skl sprite planes. And drop a bunch of unnecessary includes while at it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230314130255.23273-10-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
2023-03-17drm/i915: Relocate intel_plane_check_src_coordinates()Ville Syrjälä
Move intel_plane_check_src_coordinates() from the pre-skl sprite plane specific code to a more suitable place for common plane code. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230314130255.23273-9-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
2023-03-17drm/i915: Clean up skl+ plane alpha bitsVille Syrjälä
Convert a few more skl+ plane registers to REG_BIT() & co. Somehow thse were missed during the earlier cleanup. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230314130255.23273-8-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
2023-03-17drm/i915: Define vlv/chv sprite plane SURFLIVE registersVille Syrjälä
Might as well complete the SURFLIVE register definitions for all platforms/plane types. We are only missing the VLV/CHV sprite planes. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230314130255.23273-7-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
2023-03-17drm/i915: Define skl+ universal plane SURFLIVE registersVille Syrjälä
Add the definitions for the skl+ univerals plane SURFLIVE registers. Despite not being used for anything real these came in suprisingly handy during some DSB debugging recently, so having the defines around can be useful. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230314130255.23273-6-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
2023-03-17drm/i915: Program VLV/CHV PIPE_MSA_MISC registerVille Syrjälä
VLV/CHV have an extra register to configure some stereo3d signalling details via DP MSA. Make sure we reset that register to zero (since we don't do any stereo3d stuff). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230314130255.23273-5-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
2023-03-17drm/i915: Define more pipe timestamp registersVille Syrjälä
Add definitions for various pipe timestamp registers: - frame timestamp (last start of vblank) (g4x+), already had this defined - flip timestamp (when SURF was last written) (g4x+) - flipdone timestamp (when last flipdone was signalled) (tgl+) Note that on pre-tgl the flip related timestamps are only updated for primary plane flips, but on tgl+ we can select which plane updates them (via PIPE_MISC2). Let's define those related bits as well. Curiously VLV/CHV do not have the frame/flip timestamp registers, despite all the other related registers being inherited from g4x. This means we can get rid of the pipe_offsets[] usage for these, and thus the implicit dev_priv is gone as well. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230314130255.23273-4-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
2023-03-17drm/i915: s/PIPEMISC/PIPE_MISC/Ville Syrjälä
This PIPEMISC vs. PIPE_MISC inconsitency is ugly. Unify the naming (PIPE_MISC is also what bspec has always called it). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230314130255.23273-3-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
2023-03-17drm/i915: Stop using pipe_offsets[] for PIPE_MISC*Ville Syrjälä
The PIPE_MISC registers don't exist on pre-bdw hardware, so there is no point in using pipe_offsets[] for them. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230314130255.23273-2-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
2023-03-16drm/i915/display: ignore link training failures in CIVinod Govindapillai
If the ignore long HPD flag is set, ignore the link training failures as well. Because of spurious HPDs, some unexpected link training failures are happening while executing IGT test cases. Ignore the link training failures for the time being if the long HPDs are also ignored in the environments like CI. Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230215083832.287519-3-vinod.govindapillai@intel.com
2023-03-16drm/i915/display: ignore long HPDs based on a flagVinod Govindapillai
Some panels generate long HPD events even while connected to the port. This cause some unexpected CI execution issues. A new flag is added to track if such spurious long HPDs can be ignored and are not processed further if the flag is set. Debugfs entry is added to control the ignore long hpd flag. v2: Address patch styling comments (Jani Nikula) v3: Ignoring the HPD moved to hotplug handler and now applies to all types of outputs (Imre Deak) v4: use debugfs_create_bool and squash patches (Jani Nikula) Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230215083832.287519-2-vinod.govindapillai@intel.com
2023-03-16drm/i915/opregion: Fix CONFIG_ACPI=n builds adding missing ↵Imre Deak
intel_opregion_cleanup() prototype Add the missing intel_opregion_cleanup() prototype fixing CONFIG_ACPI=n builds. Fixes: 3e226e4a2180 ("drm/i915/opregion: Cleanup opregion after errors during driver loading") Cc: Jani Nikula <jani.nikula@intel.com> Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Link: https://lore.kernel.org/oe-kbuild-all/202303141610.6L1VO7Gw-lkp@intel.com/ Signed-off-by: Imre Deak <imre.deak@intel.com>
2023-03-15drm/i915: Don't send idle pattern after DP2.0 link trainingVille Syrjälä
Bspec calls us to select pattern 2 after link training for DP 2.0. Let's do that... by doing nothing because we will be transmitting pattern 2 at the end of the link training already. Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230308212627.7601-2-ville.syrjala@linux.intel.com
2023-03-15drm/i915: Don't switch to TPS1 when disabling DP_TP_CTLVille Syrjälä
AFAICS Bspec has never asked us to switch to TPS1 when *disabling* DP_TP_CTL. Let's stop doing that in case it confuses something. We do have to switch before we *enable* DP_TP_CTL, but that is already being handled correctly. v2: Do the same for FDI v3: Rebase Reviewed-by: Imre Deak <imre.deak@intel.com> #v1 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230308212627.7601-1-ville.syrjala@linux.intel.com
2023-03-14drm/i915/dp: Don't roundup max bpp, while computing compressed bppAnkit Nautiyal
While computing compressed bpp, maximum value of bits_per_pixel is calculated that can be supported with the given link configuration for a given mode. Avoid rounding up of this max bits_per_pixel. Also improve documentation for computing max bits_per_pixel. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230223115509.3980226-1-ankit.k.nautiyal@intel.com
2023-03-14drm/i915/debugfs: move IPS debugfs to hsw_ips.cJani Nikula
Follow the style of placing debugfs next to the implementation. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230302161617.2978821-1-jani.nikula@intel.com
2023-03-10drm/i915: Reject wm levels that exceed vblank timeVille Syrjälä
The pipe needs a certain amount of time during vblank to prefill sufficiently. If the vblank is too short the relevant watermark level must be disabled. Start implementing the necessary calculations to check this. Scaler and DSC prefill are left out for now as handling those is not entirely trivial. Also the PSR latency reporting override chicken bits would need to be correctly configured based on the results of these calculations. Just add some FIXMEs for now. TODO: bspec isn't exactly crystal clear in its explanations so quite a few open questions remain... v2: Skip inacive pipes Handle SAGV latency v3: Rebase v4: Fix handling of disabled wm levels (latency == 0) Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230306164854.25928-1-ville.syrjala@linux.intel.com
2023-03-10drm/i915: Extract skl_wm_latency()Ville Syrjälä
Extract the skl+ wm latency determination into a small helper so that everyone has the same idea what the latency should be. This introduces a slight functional change in that skl_cursor_allocation() will now start to account for the extra 4 usec that the kbk/cfl/cml IPC w/a adds. v2: Rebase Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301162449.26672-2-ville.syrjala@linux.intel.com
2023-03-10drm/i915/opregion: Register display debugfs later, after initialization stepsImre Deak
Move the display debugfs registration later, after initializing steps for opregion/acpi/audio. These latter ones don't depend on the debugfs entries, OTOH some debugfs entries may depend on the initialized state. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230308162503.3219200-3-imre.deak@intel.com
2023-03-10drm/i915/opregion: Cleanup opregion after errors during driver loadingImre Deak
Clean up the opregion state if something fails after intel_opregion_setup() is called. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230308162503.3219200-2-imre.deak@intel.com
2023-03-10drm/i915/opregion: Fix opregion setup during system resume on platforms ↵Imre Deak
without display Atm, during system resume, the driver updates the display connector information required by the opregion video extensions during system resume, on platforms both with and without display being present. On !HAS_DISPLAY platforms this will result in the crash with the stack trace below, since the driver's connector state is not initialized on those. Bspec doesn't specify when each of the opregion functionality is supported (depending on the presence of display), however we can presume that none of the video extensions, nor the ACPI _DSM functions are supported on !HAS_DISPLAY platforms; accordingly skip the corresponding opregion/ACPI setup on those (also matching the Windows driver in this). Keep sending the opregion notification about suspending/resuming the whole adapter (vs. the display only which is a separate power state notification) on all platforms, similarly to runtime suspend/resume. This fixes the following: Oops: 0000 [#1] PREEMPT SMP NOPTI CPU: 4 PID: 1443 Comm: kworker/u40:55 Tainted: G U 6.2.0-rc8+ #58 Hardware name: LENOVO 82VB/LNVNB161216, BIOS KMCN09WW 04/26/2022 Workqueue: events_unbound async_run_entry_fn RIP: 0010:drm_connector_list_iter_next+0x4f/0xb0 Call Trace: <TASK> intel_acpi_device_id_update+0x80/0x160 [i915] intel_opregion_resume+0x2f/0x1e0 [i915] ? dg2_init_clock_gating+0x49/0xf0 [i915] i915_drm_resume+0x137/0x190 [i915] ? __pfx_pci_pm_resume+0x10/0x10 dpm_run_callback+0x47/0x150 Cc: iczero <iczero@hellomouse.net> Reported-and-tested-by: iczero <iczero@hellomouse.net> References: https://gitlab.freedesktop.org/drm/intel/-/issues/8015 Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230308162503.3219200-1-imre.deak@intel.com
2023-03-10drm/i915: Preserve crtc_state->inherited during state clearingVille Syrjälä
intel_crtc_prepare_cleared_state() is unintentionally losing the "inherited" flag. This will happen if intel_initial_commit() is forced to go through the full modeset calculations for whatever reason. Afterwards the first real commit from userspace will not get forced to the full modeset path, and thus eg. audio state may not get recomputed properly. So if the monitor was already enabled during boot audio will not work until userspace itself does an explicit full modeset. Cc: stable@vger.kernel.org Tested-by: Lee Shawn C <shawn.c.lee@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230223152048.20878-1-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>
2023-03-10drm/i915: Ensure DSC has enough BW and stays within HW limitsStanislav Lisovskiy
We currently have an issue with some BPPs when using DSC. According to the HW team, the reason is that a single VDSC engine instance has some BW limitations that must be accounted for. So, whenever we approach around 90% of the CDCLK, a second VDSC engine has to be used. This always means using two slices. However, in our current code, the amount of slices is calculated independently of whether we need to enable the second VDSC engine or not. This leads to some logical issues when, according to the pixel clock needs, we need to enable the second VDSC engine. But as we calculated previously that we can only use a single slice, we can't do that and fail. So, we need to fix that so that the number of VDSC engines enabled should depend on the number of slices, and the number of slices should also depend on BW requirements. Lastly, we didn't have BPP limitation for ADLP/MTL/DG2 implemented, which says that DSC output BPPs can only be chosen within the range of 8 to 27 (BSpec 49259). All of this applied together allows us to fix existing FIFO underruns, which we have in many DSC tests. v2: - Replace min with clamp_t(Jani Nikula) - Fix commit message(Swati Sharma) - Added "Closes"(Swati Sharma) BSpec: 49259 HSDES: 18027167222 Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8231 Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230306080401.22552-1-stanislav.lisovskiy@intel.com
2023-03-09drm/i915/dmc: Load DMC on MTLMadhumitha Tolakanahalli Pradeep
Add support to load DMC on MTL. According to the spec and based on tests done on real hardware, 0x7000 is a reasonable size limit that covers each possible payload. v2: - Tighten payload size limit. (Matt, Rodrigo) - Use a better name for the defined payload limit. (Rodrigo) Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230307195111.90767-1-gustavo.sousa@intel.com
2023-03-09drm/i915/display/mtl: Program latch to phy resetJosé Roberto de Souza
Latch reset of phys during DC9 and when driver is unloaded to avoid phy reset. Specification ask us to program it closer to the step that enables DC9 in DC_STATE_EN but doing this way allow us to sanitize the phy latch during driver load. BSpec: 49197 Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301201053.928709-6-radhakrishna.sripada@intel.com
2023-03-09drm/i915/fbdev: lock the fbdev obj before vma pinTejas Upadhyay
lock the fbdev obj before calling into i915_vma_pin_iomap(). This helps to solve below : <7>[ 93.563308] i915 0000:00:02.0: [drm:intelfb_create [i915]] no BIOS fb, allocating a new one <4>[ 93.581844] ------------[ cut here ]------------ <4>[ 93.581855] WARNING: CPU: 12 PID: 625 at drivers/gpu/drm/i915/gem/i915_gem_pages.c:424 i915_gem_object_pin_map+0x152/0x1c0 [i915] Fixes: f0b6b01b3efe ("drm/i915: Add ww context to intel_dpt_pin, v2.") Cc: Chris Wilson <chris.p.wilson@intel.com> Cc: Matthew Auld <matthew.auld@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301201053.928709-5-radhakrishna.sripada@intel.com
2023-03-09drm/i915/mtl: Fix Wa_16015201720 implementationRadhakrishna Sripada
The commit 2357f2b271ad ("drm/i915/mtl: Initial display workarounds") extended the workaround Wa_16015201720 to MTL. However the registers that the original WA implemented moved for MTL. Implement the workaround with the correct register. v3: Skip clock gating for pipe C, D DMC's and fix the title Fixes: 2357f2b271ad ("drm/i915/mtl: Initial display workarounds") Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301201053.928709-2-radhakrishna.sripada@intel.com
2023-03-07drm/i915: Get rid of the gm45 HPD live state nonsenseVille Syrjälä
The idea that ctg uses different HPD live state bits is total nonsense, at least on my machine (Dell Latitude E5400). The only reason DP-B even works on my ctg is that DP-D live state is stuck high, even though there is no physical DP-D port. So when the detect checks DP-B live state it sees the stuck live state of DP-D instead. If I hack the driver to not register DP-D at all, and thus we never enabe DP-D HPD, DP-B stops working as well. Just to put some conclusive evidence into this mess, here are the actual hotplug register values for each port: Everything disconnected: PORT_HOTPLUG_EN (0x00061110): 0x00000000 PORT_HOTPLUG_STAT (0x00061114): 0x00000000 PORT_HOTPLUG_EN (0x00061110): 0x08000000 PORT_HOTPLUG_STAT (0x00061114): 0x08000000 PORT_HOTPLUG_EN (0x00061110): 0x10000000 PORT_HOTPLUG_STAT (0x00061114): 0x00000000 PORT_HOTPLUG_EN (0x00061110): 0x20000000 PORT_HOTPLUG_STAT (0x00061114): 0x00000000 Only port B connected: PORT_HOTPLUG_EN (0x00061110): 0x00000000 PORT_HOTPLUG_STAT (0x00061114): 0x00000000 PORT_HOTPLUG_EN (0x00061110): 0x08000000 PORT_HOTPLUG_STAT (0x00061114): 0x08000000 PORT_HOTPLUG_EN (0x00061110): 0x10000000 PORT_HOTPLUG_STAT (0x00061114): 0x00000000 PORT_HOTPLUG_EN (0x00061110): 0x20000000 PORT_HOTPLUG_STAT (0x00061114): 0x20000000 Only port C connected: PORT_HOTPLUG_EN (0x00061110): 0x00000000 PORT_HOTPLUG_STAT (0x00061114): 0x00000000 PORT_HOTPLUG_EN (0x00061110): 0x08000000 PORT_HOTPLUG_STAT (0x00061114): 0x08000000 PORT_HOTPLUG_EN (0x00061110): 0x10000000 PORT_HOTPLUG_STAT (0x00061114): 0x10000000 PORT_HOTPLUG_EN (0x00061110): 0x20000000 PORT_HOTPLUG_STAT (0x00061114): 0x00000000 So the enable bit and live state bit always match 1:1. Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230302161013.29213-4-ville.syrjala@linux.intel.com
2023-03-07drm/i915: Fix SKL DDI A digital port .connected()Ville Syrjälä
SKL doesn't have any north DE hotplug stuff. Currently we're trying to read DDI A live state from the BDW north DE bit, instead of the approproate south DE bit. Fix it. And for good measure clear the pointer to the north hpd pin array, so that we'll actually notice if some other place is also using the wrong thing. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230302161013.29213-3-ville.syrjala@linux.intel.com
2023-03-07drm/i915: Populate dig_port->connected() before connector initVille Syrjälä
We'll need dig_port->connected() to be there for a HPD live state check during eDP connector probing. Reorder intel_ddi_init() accordingly. g4x_dp_init() is already fine. v2: Fix comment style while at it Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230302161013.29213-2-ville.syrjala@linux.intel.com
2023-03-07drm/i915: Bump VBT version for expected child dev size checkVille Syrjälä
The most modern VBT I've observed in the wild is version 250. The child dev size hasn't changed since version 216, so bump the version number in the expected child dev size check. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230306154419.23207-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2023-03-06drm/i915/rps: split out display rps parts to a separate fileJani Nikula
Split out the RPS parts so they can be conditionally compiled out later. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230302164936.3034161-1-jani.nikula@intel.com
2023-03-06drm/i915/dmc: mass rename dev_priv to i915Jani Nikula
Follow the contemporary convention for struct drm_i915_private * naming. Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301122944.1298929-5-jani.nikula@intel.com
2023-03-06drm/i915/dmc: allocate dmc structure dynamicallyJani Nikula
sizeof(struct intel_dmc) > 1024 bytes, allocated on all platforms as part of struct drm_i915_private, whether they have DMC or not. Allocate struct intel_dmc dynamically, and hide all the dmc details behind an opaque pointer in intel_dmc.c. Care must be taken to take into account all cases: DMC not supported on the platform, DMC supported but not initialized, and DMC initialized but not loaded. For the second case, we need to move the wakeref out of struct intel_dmc. v2: - Rebase to kzalloc dmc after runtime pm get (Imre) Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301122944.1298929-4-jani.nikula@intel.com
2023-03-06drm/i915/dmc: add i915_to_dmc() and dmc->i915 and use themJani Nikula
Start preparing for dynamically allocated struct intel_dmc by adding i915_to_dmc() and dmc->i915, and using them. Take the future NULL dmc pointer into account already now, and add separate logging for initialization in the DMC debugfs. v3: - Obtain runtime pm reference first (Imre) v2: - Don't reduce debugfs output (Imre) Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301122944.1298929-3-jani.nikula@intel.com
2023-03-06drm/i915/dmc: use has_dmc_id_fw() instead of poking dmc->dmc_info directlyJani Nikula
This will help in follow-up changes. Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301122944.1298929-2-jani.nikula@intel.com
2023-03-06drm/i915/power: move dc state members to struct i915_power_domainsJani Nikula
There's only one reference to the struct intel_dmc members dc_state, target_dc_state, and allowed_dc_mask within intel_dmc.c, begging the question why they are under struct intel_dmc to begin with. Moreover, the only references to i915->display.dmc outside of intel_dmc.c are to these members. They don't belong. Move them from struct intel_dmc to struct i915_power_domains, which seems like a more suitable place. Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301122944.1298929-1-jani.nikula@intel.com
2023-03-06drm/i915: remove unnecessary intel_pm.h includesJani Nikula
As intel_pm.[ch] used to contain much more, intel_pm.h was included in a lot of places. Many of them are now unnecessary. Remove. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ab9a7147b0cd63d95b9f27ed40615b9c9be18f84.1677678803.git.jani.nikula@intel.com
generated by cgit (git 2.34.1) at 2025-07-15 22:19:04 +0000