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2024-02-22arm64: dts: renesas: r8a779h0: Add CA76 operating pointsDuy Nguyen
Add operating points for running the Cortex-A76 CPU cores on R-Car V4M at various speeds, up to the Normal (1.0 GHz). Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/736b5836ec2b54e8b36712866309dc1b7ee1fc48.1706796979.git.geert+renesas@glider.be
2024-02-22arm64: dts: renesas: r8a779h0: Add CPU core clocksDuy Nguyen
Describe the clocks for the four Cortex-A76 CPU cores. CA76 CPU cores 0,1,2,3 are clocked by ZC0,ZC1,ZC2,ZC3. Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/c64cf6ca1590fa1a36b90a18fd70c831d5b8318e.1706796979.git.geert+renesas@glider.be
2024-02-22arm64: dts: renesas: r8a779h0: Add CPUIdle supportDuy Nguyen
Support CPUIdle for ARM Cortex-A76 on R-Car V4M. Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/848d176bdbcaf3bc44e5dae555afa9c812a19fd1.1706796979.git.geert+renesas@glider.be
2024-02-22arm64: dts: renesas: r8a779h0: Add secondary CA76 CPU coresDuy Nguyen
Complete the description of the Cortex-A76 CPU cores and L3 cache controllers on the Renesas R-Car V4M (R8A779H0) SoC, including CPU topology and PSCI support for enabling CPU cores. Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/c2a38a0da74915bf2a9171e53886c83a1c732934.1706796979.git.geert+renesas@glider.be
2024-02-22arm64: dts: renesas: r8a779h0: Add L3 cache controllerDuy Nguyen
Describe the cache configuration for the first Cortex-A76 CPU core on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/9d56a46892c5e0957d244370e6809013cf815905.1706796979.git.geert+renesas@glider.be
2024-02-22arm64: dts: renesas: r8a779h0: Add GPIO nodesCong Dang
Add device nodes for the General Purpose Input/Output (GPIO) blocks on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/d4c1c40404ab84c7e7c07612077ca1a319ae7283.1706796918.git.geert+renesas@glider.be
2024-02-22arm64: dts: renesas: gray-hawk-single: Add I2C0 and EEPROMsGeert Uytterhoeven
Enable the I2C0 bus on the Gray Hawk Single board, and describe the I2C EEPROMs present. Based on patches for Gray Hawk in the BSP by Hai Pham. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/960595394a274b675f1ec9ec1c324e4cc1ac1f77.1706796660.git.geert+renesas@glider.be
2024-02-22arm64: dts: renesas: r8a779h0: Add I2C nodesHai Pham
Add device nodes for the I2C Bus Interfaces on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/7dbbe13428273c5786ddff6ea7af6724fcdd4de8.1706796660.git.geert+renesas@glider.be
2024-02-22arm64: dts: renesas: ulcb-kf: Adapt sound 5v regulator to schematicsWolfram Sang
Sound uses the standard 5V supply, so rename the fixed regulator as such. Also add properties documenting it is always on, also during boot. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240129212350.33370-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-02-22arm64: dts: renesas: ulcb-kf: Adapt 1.8V HDMI regulator to schematicsWolfram Sang
It is named T1.8V in the schematics. Also add properties documenting it is always on, also during boot. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240129212350.33370-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-02-22arm64: dts: renesas: ulcb-kf: Add regulators for PCIe ch1Wolfram Sang
Without them, no power, so cards do not get recognized. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240129135840.28988-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-02-22arm64: dts: renesas: gray-hawk-single: Add serial console pin controlGeert Uytterhoeven
Complete the descriptions of the serial console and the external serial clock by adding pin control. Based on patches for Gray Hawk in the BSP by Hai Pham and Nghia Nguyen. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/b1eb2d3364d5ead7f7bcf7a737c5914971db64d3.1706266286.git.geert+renesas@glider.be
2024-02-22arm64: dts: renesas: r8a779h0: Add pinctrl device nodeHai Pham
Add a device node for the Pin Function Controller on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/0ab32290014b64ddbee5c9ec2808c8294d0b6192.1706266286.git.geert+renesas@glider.be
2024-02-06arm64: dts: renesas: gray-hawk-single: Enable watchdog timerGeert Uytterhoeven
Enable the watchdog timer on the Gray Hawk Single board. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/cf6effafd9e0472a457eed9d84a834abc3e1c833.1706790320.git.geert+renesas@glider.be
2024-02-06arm64: dts: renesas: r8a779h0: Add RWDT nodeMinh Le
Add a device node for the RCLK Watchdog Timer (RWDT) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Minh Le <minh.le.aj@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/43bb03f3baa87b4be8ce953b1955df6b89387e4c.1706790320.git.geert+renesas@glider.be
2024-02-06arm64: dts: renesas: Improve TMU interrupt descriptionsGeert Uytterhoeven
Add the input capture interrupt on Timer Unit instances that have it. Add "interrupt-names" properties for clarity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/5c70ad8c2ea14333616c5add31a4a958f4a47081.1705325654.git.geert+renesas@glider.be
2024-02-06ARM: dts: renesas: Improve TMU interrupt descriptionsGeert Uytterhoeven
Add the input capture interrupt on Timer Unit instances that have it. Add "interrupt-names" properties for clarity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/389a18ee2cea96726462c28463cf212330f74ee3.1705325654.git.geert+renesas@glider.be
2024-01-31arm64: dts: renesas: r9a07g043u: Add CSI and CRU nodesBiju Das
Add CSI and CRU nodes r9a07g043 (RZ/G2UL) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240126133116.121981-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-01-31arm64: dts: renesas: Add Gray Hawk Single board supportGeert Uytterhoeven
Add initial support for the Renesas Gray Hawk Single board, which is based on the R-Car V4M (R8A779H0) SoC: - Memory, - Crystal oscillators, - Serial console. Based on the White Hawk Single DTS, and on a patch for the Gray Hawk board stack in the BSP by Hai Pham. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/b657402113267acd57aece0b4c681b707e704455.1706194617.git.geert+renesas@glider.be
2024-01-31arm64: dts: renesas: Add Renesas R8A779H0 SoC supportHai Pham
Add initial support for the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/4107bc3d7c31932da29e671ddf4b1564ba38a84c.1706194617.git.geert+renesas@glider.be
2024-01-31Merge tag 'renesas-r8a779h0-dt-binding-defs-tag' into renesas-dts-for-v6.9Geert Uytterhoeven
Renesas R-Car V4M DT Binding Definitions Clock and Power Domain definitions for the Renesas R-Car V4M (R8A779H0) SoC, shared by driver and DT source files.
2024-01-31arm64: dts: renesas: rzg3s-smarc-som: Enable the watchdog interfaceClaudiu Beznea
Enable the watchdog interface (accessible by Cortex-A of RZ/G3S SoC) on RZ/G3S SMARC SoM. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240122111115.2861835-11-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-01-31arm64: dts: renesas: r9a08g045: Add watchdog nodeClaudiu Beznea
Add the DT node for the watchdog IP accessible by Cortex-A of RZ/G3S SoC (R9108G045). Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240122111115.2861835-10-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-01-31arm64: dts: renesas: r8a779g0: Add missing SCIF_CLK2Geert Uytterhoeven
R-Car V4H actually has two SCIF_CLK pins. The second pin provides the SCIF_CLK signal for HSCIF2 and SCIF4. Fixes: a4c31c56d2d35641 ("arm64: dts: renesas: r8a779g0: Add SCIF nodes") Fixes: 39d9dfc6fbe1860e ("arm64: dts: renesas: r8a779g0: Add remaining HSCIF nodes") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/72f20c1bf32187bd30a963cafe27252907d661f9.1705589612.git.geert+renesas@glider.be
2024-01-31dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock DefinitionsDuy Nguyen
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/11acbd2a30b58607474e9c32eb798b3a00e85e73.1706194617.git.geert+renesas@glider.be
2024-01-31dt-bindings: clock: renesas,cpg-mssr: Document R-Car V4M supportGeert Uytterhoeven
Document support for the Clock Pulse Generator (CPG) and Module Standby Software Reset (MSSR) module on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/eb3cd02b62f3ca834df079a3f1e551d9414fe42a.1706194617.git.geert+renesas@glider.be
2024-01-30dt-bindings: power: Add r8a779h0 SYSC power domain definitionsDuy Nguyen
Add power domain indices for the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/c5cbef71178cada761e9da7bcbb6f21334f93ef8.1706194617.git.geert+renesas@glider.be Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-01-30dt-bindings: power: renesas,rcar-sysc: Document R-Car V4M supportDuy Nguyen
Document support for the System Controller (SYSC) in the R-Car V4M (R8A779H0) SoC. Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/6315cbd0b6e9b92a7914d98f397a2c663ad521c6.1706194617.git.geert+renesas@glider.be Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2024-01-29arm64: dts: renesas: r8a779g2: Add White Hawk Single supportGeert Uytterhoeven
The White Hawk Single board is a single-board integration of the Renesas White Hawk CPU and Breakout board stack, based on the R-Car V4H ES2.0 (R8A779G2) SoC. For now, the only visible differences compared to the board stack are: - The SoC is an updated version of R-Car V4H (R8A779G0), - The serial console uses an FT2232H instead of a CP2102 USB-UART bridge, with CTS/RTS wired. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/2b8d37949c17cca170c1d9e97f10a100b20c5cd9.1706192990.git.geert+renesas@glider.be
2024-01-29arm64: dts: renesas: Add Renesas R8A779G2 SoC supportGeert Uytterhoeven
Add support for the Renesas R-Car V4H ES2.0 (R8A779G2) SoC, which is an updated version of the R-Car V4H (R8A779G0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/4f773dbb66af5da51d1e171424ec8f97ee933b36.1706192990.git.geert+renesas@glider.be
2024-01-29arm64: dts: renesas: white-hawk: Factor out common partsGeert Uytterhoeven
Factor out the parts on the White Hawk BreakOut board that are also present on the White Hawk Single board, so they can be reused when introducing support for the latter. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/8c05b4d283b5d765fbc6f64cee9a247cded29409.1706192990.git.geert+renesas@glider.be
2024-01-29arm64: dts: renesas: white-hawk-cpu: Factor out common partsGeert Uytterhoeven
Factor out the parts on the White Hawk CPU board that are also present on the White Hawk Single board, so they can be reused when introducing support for the latter. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/50676e7e9ac1c50ab450c030481f60ece4c3947e.1706192990.git.geert+renesas@glider.be
2024-01-29arm64: dts: renesas: white-hawk: Add SoC name to top-level commentGeert Uytterhoeven
The White Hawk CPU and BreakOut board DTS is specific to R-Car V4H. Document it in the top-level comment. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/de81db7ca38c8f4737092bdac6891e9db4bb9bd6.1706192990.git.geert+renesas@glider.be
2024-01-29arm64: dts: renesas: white-hawk: Drop SoC parts from sub boardsGeert Uytterhoeven
The White Hawk CSI/DSI and RAVB/Ethernet(1000Base-T1) sub boards are not specific to R-Car V4H. Hence rename their DTS file names to drop the "r8a779g0-" prefix, and remove any references to R-Car V4H. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/f89613d0df04cfa6196f8797fe655cf7cec812de.1706192990.git.geert+renesas@glider.be
2024-01-29arm64: dts: renesas: white-hawk-cpu: Restore sort orderGeert Uytterhoeven
Alphabetical by node name. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/f375293d6e21659ee30a86e2b46e4998a75ea3b5.1706192990.git.geert+renesas@glider.be
2024-01-29arm64: dts: renesas: r8a779g0: Add standalone White Hawk CPU supportGeert Uytterhoeven
The White Hawk CPU board can be used standalone, without connecting it to the White Hawk BreakOut board. Add a DTS file for supporting this use case. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/95ac53e7f2bc42402eb411ad7f64a66864a3de01.1706192990.git.geert+renesas@glider.be
2024-01-29arm64: dts: renesas: ulcb-kf: Add node for GNSSWolfram Sang
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240117131807.24997-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-01-29arm64: dts: renesas: ulcb-kf: Drop duplicate 3.3v regulatorsWolfram Sang
Schematics say that all these 3.3v sources are driven by "D3.3V". We have a regulator for it already in ulcb.dtsi. Use it instead. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240117131807.24997-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-01-22arm64: dts: renesas: r8a779g0: Restore sort orderGeert Uytterhoeven
Numerical by unit address, alphabetical by node name. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/f00ef274a73c8fd60f940a1649423a8927b9ae8a.1705324708.git.geert+renesas@glider.be
2024-01-22ARM: dts: renesas: r8a73a4: Fix thermal parent clockGeert Uytterhoeven
According to Table 8.1, "Summary of Module Power, Reset condition and Clock assignment" of the R-Mobile APE6 Hardware Manual Rev. 0.7, the parent clock of the thermal sensor clock is the Common Peripheral (CP) clock, which runs at 13 MHz (main clock / 2). As the R-Car Thermal driver does not use the clock rate, this change has no functional impact. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/aac49d67d7a38230875543d49e84fcca587fb9e1.1705315614.git.geert+renesas@glider.be
2024-01-22ARM: dts: renesas: r8a73a4: Add cp clockGeert Uytterhoeven
Add the Common Peripheral (CP) clock, which is driven by the main clock / 2 during normal system operation, but may be driven by EXTALR during early system boot, when SYSCLK_EN is still low. As the latter is irrelevant to Linux, just model it as a fixed clock driven from main_div2_clk. Switch all users of main_div2_clk that are documented to be clocked by the CP clock to cp_clk, to better reflect the actual clock topology. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/f9826b0755207a1e16871c17daca109fb11f3868.1705315614.git.geert+renesas@glider.be
2024-01-22ARM: dts: renesas: r8a73a4: Fix external clocks and clock rateGeert Uytterhoeven
External clocks should be defined as zero-Hz clocks in the SoC .dtsi, and overridden in the board .dts when present. Correct the clock rate of extal1 from 25 to 26 MHz, to match the crystal oscillator present on the APE6-EVM board. Fixes: a76809a329d6ebae ("ARM: shmobile: r8a73a4: Common clock framework DT description") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/1692bc8cd465d62168cbf110522ad62a7af3f606.1705315614.git.geert+renesas@glider.be
2024-01-22arm64: dts: renesas: rzg3s-smarc: Add gpio keysClaudiu Beznea
RZ SMARC Carrier II board has 3 user buttons called USER_SW1, USER_SW2, USER_SW3. Add a DT node in device tree to propertly instantiate the gpio-keys driver for these buttons. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231227130810.2744550-1-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-01-21Linux 6.8-rc1Linus Torvalds
2024-01-21Merge tag 'bcachefs-2024-01-21' of https://evilpiepirate.org/git/bcachefsLinus Torvalds
Pull more bcachefs updates from Kent Overstreet: "Some fixes, Some refactoring, some minor features: - Assorted prep work for disk space accounting rewrite - BTREE_TRIGGER_ATOMIC: after combining our trigger callbacks, this makes our trigger context more explicit - A few fixes to avoid excessive transaction restarts on multithreaded workloads: fstests (in addition to ktest tests) are now checking slowpath counters, and that's shaking out a few bugs - Assorted tracepoint improvements - Starting to break up bcachefs_format.h and move on disk types so they're with the code they belong to; this will make room to start documenting the on disk format better. - A few minor fixes" * tag 'bcachefs-2024-01-21' of https://evilpiepirate.org/git/bcachefs: (46 commits) bcachefs: Improve inode_to_text() bcachefs: logged_ops_format.h bcachefs: reflink_format.h bcachefs; extents_format.h bcachefs: ec_format.h bcachefs: subvolume_format.h bcachefs: snapshot_format.h bcachefs: alloc_background_format.h bcachefs: xattr_format.h bcachefs: dirent_format.h bcachefs: inode_format.h bcachefs; quota_format.h bcachefs: sb-counters_format.h bcachefs: counters.c -> sb-counters.c bcachefs: comment bch_subvolume bcachefs: bch_snapshot::btime bcachefs: add missing __GFP_NOWARN bcachefs: opts->compression can now also be applied in the background bcachefs: Prep work for variable size btree node buffers bcachefs: grab s_umount only if snapshotting ...
2024-01-21Merge tag 'timers-core-2024-01-21' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull timer updates from Thomas Gleixner: "Updates for time and clocksources: - A fix for the idle and iowait time accounting vs CPU hotplug. The time is reset on CPU hotplug which makes the accumulated systemwide time jump backwards. - Assorted fixes and improvements for clocksource/event drivers" * tag 'timers-core-2024-01-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: tick-sched: Fix idle and iowait sleeptime accounting vs CPU hotplug clocksource/drivers/ep93xx: Fix error handling during probe clocksource/drivers/cadence-ttc: Fix some kernel-doc warnings clocksource/drivers/timer-ti-dm: Fix make W=n kerneldoc warnings clocksource/timer-riscv: Add riscv_clock_shutdown callback dt-bindings: timer: Add StarFive JH8100 clint dt-bindings: timer: thead,c900-aclint-mtimer: separate mtime and mtimecmp regs
2024-01-21Merge tag 'powerpc-6.8-2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull powerpc fixes from Aneesh Kumar: - Increase default stack size to 32KB for Book3S Thanks to Michael Ellerman. * tag 'powerpc-6.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: powerpc/64s: Increase default stack size to 32KB
2024-01-21bcachefs: Improve inode_to_text()Kent Overstreet
Add line breaks - inode_to_text() is now much easier to read. Signed-off-by: Kent Overstreet <kent.overstreet@linux.dev>
2024-01-21bcachefs: logged_ops_format.hKent Overstreet
Signed-off-by: Kent Overstreet <kent.overstreet@linux.dev>
2024-01-21bcachefs: reflink_format.hKent Overstreet
Signed-off-by: Kent Overstreet <kent.overstreet@linux.dev>
generated by cgit (git 2.34.1) at 2025-07-15 11:32:21 +0000