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2023-01-18arm64: dts: qcom: sm8450: Allow both GIC-ITS and internal MSI controllerManivannan Sadhasivam
The devicetree should specify both MSI implementations and the OS/driver should choose the one based on the platform requirements. Currently, Linux DWC driver will choose GIC-ITS over the internal MSI controller. Fixes: a11bbf6adef4 ("arm64: dts: qcom: sm8450: Use GIC-ITS for PCIe0 and PCIe1") Suggested-by: Rob Herring <robh@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111123004.21048-2-manivannan.sadhasivam@linaro.org
2023-01-18arm64: dts: qcom: sm8550-mtp: Add USB PHYs and HC nodesAbel Vesa
Enable USB HC and PHYs nodes on SM8550 MTP board. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230119004533.1869870-3-abel.vesa@linaro.org
2023-01-18arm64: dts: qcom: sm8550: Add USB PHYs and controller nodesAbel Vesa
Add USB host controller and PHY nodes. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230119004533.1869870-2-abel.vesa@linaro.org
2023-01-18arm64: dts: qcom: sm8250: drop unused properties from tx-macroKrzysztof Kozlowski
Neither qcom,sm8250-lpass-tx-macro bindings nor the driver use "clock-frequency" and address/size cells properties. sm8250-mtp.dtb: txmacro@3220000: Unevaluated properties are not allowed ('clock-frequency', '#address-cells', '#size-cells' were unexpected) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230109112221.102473-4-krzysztof.kozlowski@linaro.org
2023-01-18arm64: dts: qcom: sm8250: drop unused clock-frequency from wsa-macroKrzysztof Kozlowski
Neither qcom,sm8250-lpass-wsa-macro bindings nor the driver use "clock-frequency" property. sm8250-hdk.dtb: codec@3240000: Unevaluated properties are not allowed ('clock-frequency' was unexpected) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230109112221.102473-3-krzysztof.kozlowski@linaro.org
2023-01-18arm64: dts: qcom: align OPP table node name with DT schemaKrzysztof Kozlowski
Bindings expect OPP tables to start with "opp-table". Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230109112221.102473-2-krzysztof.kozlowski@linaro.org
2023-01-18arm64: dts: qcom: rename mdp nodes to display-controllerDmitry Baryshkov
Follow the schema change and rename mdp nodes to generic name 'display-controller'. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230109051402.317577-6-dmitry.baryshkov@linaro.org
2023-01-18arm64: dts: qcom: rename mdss nodes to display-subsystemDmitry Baryshkov
Follow the schema change and rename mdss nodes to generic name 'display-subsystem'. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230109051402.317577-4-dmitry.baryshkov@linaro.org
2023-01-18arm64: dts: qcom: add SoC specific compat strings to mdp5 nodesDmitry Baryshkov
Add SoC-specific compat string to the MDP5 device nodes to ease distinguishing between various platforms. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230109050152.316606-5-dmitry.baryshkov@linaro.org
2023-01-18arm64: dts: qcom: ipq8074: correct USB3 QMP PHY-s clock output namesRobert Marko
It seems that clock-output-names for the USB3 QMP PHY-s where set without actually checking what is the GCC clock driver expecting, so clock core could never actually find the parents for usb0_pipe_clk_src and usb1_pipe_clk_src clocks in the GCC driver. So, correct the names to be what the driver expects so that parenting works. Before: gcc_usb0_pipe_clk_src 0 0 0 125000000 0 0 50000 Y gcc_usb1_pipe_clk_src 0 0 0 125000000 0 0 50000 Y After: usb3phy_0_cc_pipe_clk 1 1 0 125000000 0 0 50000 Y usb0_pipe_clk_src 1 1 0 125000000 0 0 50000 Y gcc_usb0_pipe_clk 1 1 0 125000000 0 0 50000 Y usb3phy_1_cc_pipe_clk 1 1 0 125000000 0 0 50000 Y usb1_pipe_clk_src 1 1 0 125000000 0 0 50000 Y gcc_usb1_pipe_clk 1 1 0 125000000 0 0 50000 Y Fixes: 5e09bc51d07b ("arm64: dts: ipq8074: enable USB support") Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230108130440.670181-2-robimarko@gmail.com
2023-01-18arm64: dts: qcom: Add device tree for Samsung Galaxy Tab A 8.0 (2015)Siddharth Manthan
Galaxy Tab A 8.0 is a tablet, very similar to Tab A 9.7 with major differences being the display and touchscreen. Add it's devicetree reusing a common dtsi from gt510. Signed-off-by: Siddharth Manthan <siddharth.manthan@gmail.com> [Squashed multiple commits] Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Nikita Travkin <nikita@trvn.ru> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230107141911.47229-4-nikita@trvn.ru
2023-01-18arm64: dts: qcom: Add device tree for Samsung Galaxy Tab A 9.7 (2015)Jasper Korten
The Galaxy Tab A 9.7 (2015) is a Snapdragon 410 based tablet. This commit introduces basic support for the tablet including the following features: - SDHCI (internal and external storage) - USB Device Mode - UART - Regulators - WCNSS (WiFi/BT) - GPIO keys - Fuel gauge - Touchscreen - Accelerometer Part of the DT is split out into a common dtsi since the tablet shares majority of the design with another variant having a different screen size. Signed-off-by: Jasper Korten <jja2000@gmail.com> Co-developed-by: Siddharth Manthan <siddharth_manthan@outlook.com> Signed-off-by: Siddharth Manthan <siddharth_manthan@outlook.com> Co-developed-by: Nikita Travkin <nikita@trvn.ru> Signed-off-by: Nikita Travkin <nikita@trvn.ru> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230107141911.47229-3-nikita@trvn.ru
2023-01-18arm64: dts: qcom: sc8280xp: add rng device tree nodeBrian Masney
Add the necessary device tree node for qcom,prng-ee so we can use the hardware random number generator. This functionality was tested on a SA8540p automotive development board using kcapi-rng from libkcapi. Signed-off-by: Brian Masney <bmasney@redhat.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103182229.37169-11-bmasney@redhat.com
2023-01-18arm64: dts: qcom: sc8280xp: add aliases for i2c4 and i2c21Brian Masney
Add aliases for i2c4 and i2c21 to the crd and x13s DTS files so that what's exposed to userspace doesn't change in the future if additional i2c buses are enabled on these platforms. Signed-off-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103182229.37169-10-bmasney@redhat.com
2023-01-18arm64: dts: qcom: sa8540p-ride: add i2c nodesBrian Masney
Add the necessary nodes in order to get i2c0, i2c1, i2c12, i2c15, and i2c18 functioning on the automotive board and exposed to userspace. This work was derived from various patches that Qualcomm delivered to Red Hat in a downstream kernel. This change was validated by using i2c-tools 4.3.3 on CentOS Stream 9: [root@localhost ~]# i2cdetect -l i2c-0 i2c Geni-I2C I2C adapter i2c-1 i2c Geni-I2C I2C adapter i2c-12 i2c Geni-I2C I2C adapter i2c-15 i2c Geni-I2C I2C adapter i2c-18 i2c Geni-I2C I2C adapter [root@localhost ~]# i2cdetect -a -y 15 Warning: Can't use SMBus Quick Write command, will skip some addresses 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 10: 20: 30: -- -- -- -- -- -- -- -- 40: 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: 70: Signed-off-by: Brian Masney <bmasney@redhat.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Shazad Hussain <quic_shazhuss@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103182229.37169-9-bmasney@redhat.com
2023-01-18arm64: dts: qcom: sc8280xp: add missing spi nodesBrian Masney
Add the missing nodes for the spi buses that's present on this SoC. This work was derived from various patches that Qualcomm delivered to Red Hat in a downstream kernel. Signed-off-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103182229.37169-8-bmasney@redhat.com
2023-01-18arm64: dts: qcom: sc8280xp: add missing i2c nodesBrian Masney
Add the missing nodes for the i2c buses that's present on this SoC. This work was derived from various patches that Qualcomm delivered to Red Hat in a downstream kernel. Signed-off-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103182229.37169-7-bmasney@redhat.com
2023-01-18arm64: dts: qcom: sc8280xp: rename qup0_i2c4 to i2c4Brian Masney
In preparation for adding the missing SPI and I2C nodes to sc8280xp.dtsi, it was decided to rename all of the existing qupX_ uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead and rename qup0_i2c4 to i2c4. Note that some nodes are moved in the file by this patch to preserve the expected sort order in the file. Additionally, the properties within the pinctrl state node are sorted to match the expected order that's typically done in other DTs. Signed-off-by: Brian Masney <bmasney@redhat.com> Link: https://lore.kernel.org/lkml/20221212182314.1902632-1-bmasney@redhat.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103182229.37169-6-bmasney@redhat.com
2023-01-18arm64: dts: qcom: sc8280xp: rename qup2_i2c5 to i2c21Brian Masney
In preparation for adding the missing SPI and I2C nodes to sc8280xp.dtsi, it was decided to rename all of the existing qupX_ uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead and rename qup2_i2c5 to i2c21. Under the old name, this was the 5th index under qup2, which starts at index 16. Note that some nodes are moved in the file by this patch to preserve the expected sort order in the file. Additionally, the properties within the pinctrl state node are sorted to match the expected order that's typically done in other DTs. Signed-off-by: Brian Masney <bmasney@redhat.com> Link: https://lore.kernel.org/lkml/20221212182314.1902632-1-bmasney@redhat.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103182229.37169-5-bmasney@redhat.com
2023-01-18arm64: dts: qcom: sc8280xp: rename qup2_uart17 to uart17Brian Masney
In preparation for adding the missing SPI and I2C nodes to sc8280xp.dtsi, it was decided to rename all of the existing qupX_ uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead and rename qup2_uart17 to uart17. Note that some nodes are moved in the file by this patch to preserve the expected sort order in the file. Signed-off-by: Brian Masney <bmasney@redhat.com> Link: https://lore.kernel.org/lkml/20221212182314.1902632-1-bmasney@redhat.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103182229.37169-4-bmasney@redhat.com
2023-01-18arm64: dts: qcom: sm6115: Pad addresses to 8 hex digitsKonrad Dybcio
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-18-konrad.dybcio@linaro.org
2023-01-18arm64: dts: qcom: msm8994-kitakami: Pad addresses to 8 hex digitsKonrad Dybcio
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-17-konrad.dybcio@linaro.org
2023-01-18arm64: dts: qcom: sm8450: Pad addresses to 8 hex digitsKonrad Dybcio
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-16-konrad.dybcio@linaro.org
2023-01-18arm64: dts: qcom: msm8994-octagon: Pad addresses to 8 hex digitsKonrad Dybcio
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-15-konrad.dybcio@linaro.org
2023-01-18arm64: dts: qcom: sc7280: Pad addresses to 8 hex digitsKonrad Dybcio
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-14-konrad.dybcio@linaro.org
2023-01-18arm64: dts: qcom: sc7180: Pad addresses to 8 hex digitsKonrad Dybcio
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-13-konrad.dybcio@linaro.org
2023-01-18arm64: dts: qcom: sm8350: Pad addresses to 8 hex digitsKonrad Dybcio
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-12-konrad.dybcio@linaro.org
2023-01-18arm64: dts: qcom: sm8250: Pad addresses to 8 hex digitsKonrad Dybcio
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-11-konrad.dybcio@linaro.org
2023-01-18arm64: dts: qcom: sdm845: Pad addresses to 8 hex digitsKonrad Dybcio
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-10-konrad.dybcio@linaro.org
2023-01-18arm64: dts: qcom: sm6350: Pad addresses to 8 hex digitsKonrad Dybcio
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-9-konrad.dybcio@linaro.org
2023-01-18arm64: dts: qcom: sm8150: Pad addresses to 8 hex digitsKonrad Dybcio
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-8-konrad.dybcio@linaro.org
2023-01-18arm64: dts: qcom: sc8280xp: Pad addresses to 8 hex digitsKonrad Dybcio
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-7-konrad.dybcio@linaro.org
2023-01-18arm64: dts: qcom: ipq6018: Use lowercase hexKonrad Dybcio
One value escaped my previous lowercase hexification. Take care of it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-6-konrad.dybcio@linaro.org
2023-01-18arm64: dts: qcom: ipq6018: Add/remove some newlinesKonrad Dybcio
Some lines were broken very aggresively, presumably to fit under 80 chars and some places could have used a newline, particularly between subsequent nodes. Address all that and remove redundant comments near PCIe ranges while at it so as not to exceed 100 chars needlessly. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-5-konrad.dybcio@linaro.org
2023-01-18arm64: dts: qcom: ipq6018: Sort nodes properlyKonrad Dybcio
Order nodes by unit address if one exists and alphabetically otherwise. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-4-konrad.dybcio@linaro.org
2023-01-18arm64: dts: qcom: ipq6018: Fix up indentationKonrad Dybcio
The dwc3 subnode was indented using spaces for some reason and other properties were not exactly properly indented. Fix it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-3-konrad.dybcio@linaro.org
2023-01-18arm64: dts: qcom: ipq6018: Pad addresses to 8 hex digitsKonrad Dybcio
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-2-konrad.dybcio@linaro.org
2023-01-18arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodesAbel Vesa
Enable PCIe controllers and PHYs nodes on SM8550 MTP board. Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230118230526.1499328-3-abel.vesa@linaro.org
2023-01-18arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodesAbel Vesa
Add PCIe controllers and PHY nodes. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230118230526.1499328-2-abel.vesa@linaro.org
2023-01-18arm64: dts: qcom: sm8550-mtp: enable adsp, cdsp & mdssNeil Armstrong
Add the aDSP, cDSP and MPSS firmware and "Devicetree" firmware paths for the SM8550 MTP platform. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115-topic-sm8550-upstream-dts-remoteproc-v3-3-815a1753de34@linaro.org
2023-01-18arm64: dts: qcom: sm8550: add adsp, cdsp & mdss nodesNeil Armstrong
This adds support for the aDSP, cDSP and MPSS Subsystems found in the SM8550 SoC. The aDSP, cDSP and MPSS needs: - smp2p nodes to get event back from the subsystems - remoteproc nodes with glink-edge subnodes providing all needed resources to start and run the subsystems In addition, the MPSS Subsystem needs a rmtfs_mem dedicated memory zone. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115-topic-sm8550-upstream-dts-remoteproc-v3-2-815a1753de34@linaro.org
2023-01-18arm64: dts: qcom: sm8550: Add interconnect path to SCM nodeAbel Vesa
Add the interconnect path to SCM dts node. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115-topic-sm8550-upstream-dts-remoteproc-v3-1-815a1753de34@linaro.org
2023-01-18arm64: dts: qcom: sm8550-mtp: add DSI panelNeil Armstrong
Add nodes for the Visionox VTDR6130 found on the SM8550-MTP device. TLMM states are also added for the Panel reset GPIO and Tearing Effect signal for when the panel is running in DSI Command mode. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104-topic-sm8550-upstream-dts-display-v4-3-1729cfc0e5db@linaro.org
2023-01-18arm64: dts: qcom: sm8550-mtp: enable display hardwareNeil Armstrong
Enable MDSS/DPU/DSI0 on SM8550-MTP device. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104-topic-sm8550-upstream-dts-display-v4-2-1729cfc0e5db@linaro.org
2023-01-18arm64: dts: qcom: sm8550: add display hardware devicesNeil Armstrong
Add devices tree nodes describing display hardware on SM8550: - Display Clock Controller - MDSS - MDP - two DSI controllers and DSI PHYs This does not provide support for DP controllers present on the SM8550. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104-topic-sm8550-upstream-dts-display-v4-1-1729cfc0e5db@linaro.org
2023-01-18Merge branch ↵Bjorn Andersson
'20230103-topic-sm8550-upstream-dispcc-v3-1-8a03d348c572@linaro.org' into HEAD Merge the DT binding in order to get the dispcc include file.
2023-01-18dt-bindings: clock: document SM8550 DISPCC clock controllerNeil Armstrong
Document device tree bindings for display clock controller for Qualcomm SM8550 SoC. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103-topic-sm8550-upstream-dispcc-v3-1-8a03d348c572@linaro.org
2023-01-18arm64: dts: qcom: sm8550: fix xo clock source in cpufreq-hw nodePavankumar Kondeti
Currently, available frequencies for all CPUs are appearing as 2x of the actual frequencies. Use xo clock source as bi_tcxo in the cpufreq-hw node to fix this. Signed-off-by: Pavankumar Kondeti <quic_pkondeti@quicinc.com> Tested-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230117093533.3710000-1-quic_pkondeti@quicinc.com
2023-01-18arm64: dts: qcom: msm8916-samsung-j5-common: Add MUIC supportMarkuss Broks
The MUIC installed is a part of SM5703 MFD, and it seems to work the same as the SM5502 MUIC unit. Signed-off-by: Markuss Broks <markuss.broks@gmail.com> [Apply for msm8916-samsung-j5x] Signed-off-by: Lin, Meng-Bo <linmengbo0689@protonmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230106143051.547302-1-linmengbo0689@protonmail.com
2023-01-18arm64: dts: qcom: msm8916-samsung-j5-common: Add Hall sensorLin, Meng-Bo
Samsung Galaxy J5 2015 and 2016 have a Hall sensor on GPIO pin 52. Add GPIO Hall sensor for them. Signed-off-by: Lin, Meng-Bo <linmengbo0689@protonmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230106143037.547248-1-linmengbo0689@protonmail.com
generated by cgit (git 2.34.1) at 2025-07-16 00:17:09 +0000