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2013-04-18drm/i915: Scale ring, rather than ia, frequency on HaswellChris Wilson
Haswell introduces a separate frequency domain for the ring (uncore). So where we used to increase the CPU (IA) clock with GPU busyness, we now need to scale the ring frequency directly instead. As the ring limits our memory bandwidth, it is vital for performance that when the GPU is busy, we increase the frequency of the ring to increase the available memory bandwidth. v2: Fix the algorithm to actually use the scaled gpu frequency for the ring. v3: s/max_ring_freq/min_ring_freq/ as that is what it is Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> [danvet: Add space checkpatch complained about.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: shorten debugfs output simple attributesMika Kuoppala
commit 647416f9eefe7699754b01b9fc82758fde83248c Author: Kees Cook <keescook@chromium.org> Date: Sun Mar 10 14:10:06 2013 -0700 drm/i915: use simple attribute in debugfs routines made i915_next_seqno debugfs entry to crop it's output if returned value was large enough. Using simple_attr will limit the output to 24 bytes. Fix is to strip out preamples on all simple attributes that have one. v2: Fix all simple attributes (Daniel Vetter) Cc: Kees Cook <keescook@chromium.org> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Acked-by: Kees Cook <keescook@chromium.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: Fixup pfit disabling for gen2/3Daniel Vetter
The recent rework of the pfit handling didn't take into account that the panel fitter is fixed to pipe B: commit 24a1f16de97c4cf0029d9acd04be06db32208726 Author: Mika Kuoppala <mika.kuoppala@linux.intel.com> Date: Fri Feb 8 16:35:37 2013 +0200 drm/i915: disable shared panel fitter for pipe Fix this up by properly computing the pipe the pfit is on. Also extract the logic into its own function, add a debug assert to check that the pipe is off (mostly just documentation) and add some debug output. If pipe A was disabled after pipe B was set up, the panel fitter will be disabled. Now most userspace doesn't do modesets in this order, which is why I couldn't ever reproduce this and why it took me so long to figure out. We really need hw state readout and check support for the pannel fitter ... Reported-by: Hans de Bruin <jmdebruin@xmsnet.nl> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Hans de Bruin <jmdebruin@xmsnet.nl> References: http://permalink.gmane.org/gmane.comp.freedesktop.xorg.drivers.intel/19049 Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: Fixup Oops in the pipe config computationDaniel Vetter
Yet again our current confusion between doing the modeset globally, but only having the new parameters for one crtc at a time. So that intel_set_mode essentially already does a global modeset: intel_modeset_affected_pipes compares the current state with where we want to go to (which is carefully set up by intel_crtc_set_config) and then goes through the modeset sequence for any crtc which needs updating. Now the issue is that the actual interface with the remaining code still only works on one crtc, and so we only pass in one fb and one mode. In intel_set_mode we also only compute one intel_crtc_config (which should be the one for the crtc we're doing a modeset on). The reason for that mismatch is twofold: - We want to eventually do all modeset as global state changes, so it's just infrastructure prep. - But even the old semantics can change more than one crtc when you e.g. move a connector from crtc A to crtc B, then both crtc A and B need to be updated. Usually that means one pipe is disabled and the other enabled. This is also the reason why the hack doesn't touch the disable_pipes mask. Now hilarity ensued in our kms config restore paths when we actually try to do a modeset on all crtcs: If the first crtc should be off and the second should be on, then the call on the first crtc will notice that the 2nd one should be switched on and so tries to compute the pipe_config. But due to a lack of passed-in fb (crtc 1 should be off after all) it only results in tears. This case is ridiculously easy to hit on gen2/3 where the lvds output is restricted to pipe B. Note that before the pipe_config bpp rework gen2/3 didn't care really about the fb->depth, so this is a regression brought to light with commit 4e53c2e010e531b4a014692199e978482d471c7e Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Wed Mar 27 00:44:58 2013 +0100 drm/i915: precompute pipe bpp before touching the hw But apparently Ajax also managed to blow up pch platforms, probably with some randomized configs, and pch platforms trip up over the lack of an fb even in the old code. So this actually goes back to the first introduction of the new modeset restore code in commit 45e2b5f640b3766da3eda48f6c35f088155c06f3 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Fri Nov 23 18:16:34 2012 +0100 drm/i915: force restore on lid open Fix this mess by now by justing shunting all the cool new global modeset logic in intel_modeset_affected_pipes. v2: Improve commit message and clean up all the comments in intel_modeset_affected_pipes - since the introduction of the modeset restore code they've been a bit outdated. Bugzill: https://bugzilla.redhat.com/show_bug.cgi?id=917725 Cc: stable@vger.kernel.org References: http://www.mail-archive.com/stable@vger.kernel.org/msg38084.html Tested-by: Richard Cochran <richardcochran@gmail.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: ensure single initialization and cleanup of backlight deviceJani Nikula
Backlight cleanup in the eDP connector destroy callback caused the backlight device to be removed on some systems that first initialized LVDS and then attempted to initialize eDP. Prevent multiple backlight initializations, and ensure backlight cleanup is only done once by moving it to modeset cleanup. A small wrinkle is the introduced asymmetry in backlight setup/cleanup. This could be solved by adding refcounting, but it seems overkill considering that there should only ever be one backlight device. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=55701 Signed-off-by: Jani Nikula <jani.nikula@intel.com> Tested-by: Peter Verthez <peter.verthez@skynet.be> Cc: stable@vger.kernel.org Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: don't touch the PF regs if the power well is downPaulo Zanoni
This solves some "unclaimed register" messages when booting the machine with eDP attached. V2: Rebase and add the comment requested by Daniel. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: add intel_using_power_wellPaulo Zanoni
It returns true if we've requested to turn the power well on and it's really on. It also returns true for all the previous gens. For now there's just one caller, but I'm going to add more. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: don't check inconsistent modeset state when force-restoringDaniel Vetter
It will be only consistent once we've restored all the crtcs. Since a bunch of other callers also want to just restore a single crtc, add a boolean to disable checking only where it doesn't make sense. Note that intel_modeset_setup_hw_state already has a call to intel_modeset_check_state at the end, so we don't reduce the amount of checking. v2: Try harder not to create a big patch (Chris). v3: Even smaller (still Chris). Also fix a trailing space. References: https://lkml.org/lkml/2013/3/16/60 Cc: Tomas Melin <tomas.melin@iki.fi> Cc: Richard Cochran <richardcochran@gmail.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@vger.kernel.org Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Tested-by: Tomas Melin <tomas.melin@iki.fi> Tested-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: IVB/HSW have 32 fence registerVille Syrjälä
Increase the number of fence registers to 32 on IVB/HSW. VLV however only has 16 fence registers according to the docs. Increasing the number of fences was attempted before [1], but there was some uncertainty about the maximum CPU fence number for FBC. Since then BSpec has been updated to state that there are in fact 32 fence registers, and the CPU fence number field in the SNB_DPFC_CTL_SA register is 5 bits, and the CPU fence number field in the ILK_DPFC_CONTROL register must be zero. So now it all makes sense. [1] http://lists.freedesktop.org/archives/intel-gfx/2011-October/012865.html v2: Include some background information based on the previous attempt Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: Return stored value from max freq sysfs entryMika Kuoppala
commit 4f9b2fe0441d4bdf5666a306156b5d6755de2584 Author: Ben Widawsky <ben@bwidawsk.net> Date: Fri Apr 5 14:29:22 2013 -0700 drm/i915: Better overclock support changed the sysfs read semantics for 'gt_max_freq_mhz'. By always returning overclock max instead of stored value. Fix this by returning the stored value. Separate sysfs entry should be considered for overclocking max freq. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63415 Cc: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: Remove stale codeBen Widawsky
Looks like a some remnant from a rebase. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: Increase max fence pitch limit to 256KB on IVB+Ville Syrjälä
BSpec contains several scattered notes which state that the maximum fence stride was increased to 256KB on IVB. Testing on real hardware agrees. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: Reject fence stride=0 on gen4+Ville Syrjälä
Our checks for an invalid fence stride forgot to guard against zero stride on gen4+. Fix it. v2: Avoid duplicated code (danvet) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: Configure GAM_ECOCHK appropriatly for Gen7Ville Syrjälä
IVB and HSW use different encodings for the PPGTT cacheability bits in the GAM_ECOCHK register. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: Set GAC_ECO_BITS register on Gen7+Ville Syrjälä
According to BSpec GAC_ECO_BITS register exists on Gen7 platforms as well. Configure it accordingly. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: Add ECOBITS_SNB_BITVille Syrjälä
GAC_ECO_BITS has a bit similar to GAM_ECOCHK's ECOCHK_SNB_BIT. Add the define, and enable it on SNB. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: Don't default to overclock maxBen Widawsky
Requested-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: Better overclock supportBen Widawsky
Most importantly this will allow users to set overclock frequencies in sysfs. Previously the max was limited by the RP0 max as opposed to the overclock max. This is useful if one wants to either limit the max overclock frequency, or set the minimum frequency to be in the overclock range. It also fixes an issue where if one sets the max frequency to be below the overclock max, they wouldn't be able to set back the proper overclock max. In addition I've added a couple of other bits: Show the overclock freq. as max in sysfs Print the overclock max in debugfs. Print a warning if the user sets the min frequency to be in the overclock range. In this patch I've decided to store the hw_max when we read it from the pcode at init. The reason I do this is the pcode reads can fail, and are slow. v2: Report when user requested overclocked max (Daniel) Remove when user sets min to overclock range (Daniel) Reported-by: freezer from #intel-gfx on irc Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> [danvet: Fixup the s/100MHz/50MHz/ confusion in an unrelated comment that Mika spotted.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: use lower aux clock divider on non-ULT HSWJani Nikula
Workaround to avoid intermittent aux channel failures, per spec change. v2: Don't mess with cpu dp aux divider (Paulo Zanoni) Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> [danvet: Kill spurious tab spotted by Paulo.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: Allow PPGTT enable to failBen Widawsky
I'm really not happy that we have to support this, but this will be the simplest way to handle cases where PPGTT init can fail, which I promise will be coming in the future. v2: Resolve conflicts due to patch series reordering. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: NULL aliasing_ppgtt on cleanupBen Widawsky
This will allow us to carry on if we've cleaned up the PPGTT. The usage for this is coming up - it simplifies handling a failed PPGTT init. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> [danvet: Spill the secrets about failing ppgtt init.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: Abstract PPGTT enablingBen Widawsky
Since we've already set up a nice vtable to abstract other PPGTT functions, also abstract the actual register programming to enable things. This function will probably need to change a bit as we implement real processes. v2: Resolve conflicts due to patch series reordering. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: Rework PPGTT init codeBen Widawsky
This rework will help if future platforms choose to be a bit different. Should have no functional impact. v2: Don't move around the vtable setup (Daniel) v3: Squash in the disable-by-default patch. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: Conditionally carve out GGTT PDEBen Widawsky
It only works that way on GEN6 and GEN7. Let's not assume GENn will be the same. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915/ppgtt: Set scratch page "globally"Ben Widawsky
The PPGTT scratch page is used for all gens, and doing it in the global part of our PPGTT setup makes the code a bit nicer. This was in a patch submitted earlier as part of the PPGTT cleanups. Grumpy maintainer must have missed it, and I didn't yell when appropriate. Apologies for everyone :-) v2: Update commit message Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: random checkpatch fixesBen Widawsky
There used to be other fixes in this patch but they've slowly disappeared as other parts have been fixed. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: Map registers before GTT initBen Widawsky
This will allow us to read/write registers in GTT init. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> [danvet: Fix up error handling. We really should look into devres for this stuff ...] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: Call out GEN6 PTE specificityBen Widawsky
We can assume that the PTE layout, and size changes for future generations. To avoid confusion with the existing GEN6 PTE typedef, give it a GEN6_ prefix. v2: Fixup checkpatch warning and bikeshed commit message slightly. v3: Rebase on top of Imre's for_each_sg_pages rework. v4: Fixup conflicts in patch series reordering. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: generalize pte vs. register BAR allocationBen Widawsky
All gen6+ parts so far have 1 BAR which holds both the register space and the GTT PTEs. Up until now, that was a 4MB BAR with half allocated to each. I have a strong hunch (wink, nod, wink) that future gens will also keep a similar 50-50 split though the sizes may change. To help this along change the code to obey the rule of half the total size instead of a hard-coded 2MB. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: Use MLC (l3$) for context objectsChris Wilson
Enabling context support increases SwapBuffers latency by about 20% (measured on an i7-3720qm). We can offset that loss slightly by enabling faster caching for the contexts. As they are not backed by any particular cache (such as the sampler or render caches) our only option is to select the generic mid-level cache. This reduces the latency of the swap by about 5%. Oddly this effect can be observed running smokin-guns on IVB at 1280x1024: Using BLT copies for swaps: 151.67 fps Using Render copies for swaps (unpatched): 141.70 fps With contexts disabled: 150.23 fps With contexts in L3$: 150.77 fps Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: update FDI mPHY setup codeDaniel Vetter
Bspec has been been updated and dropped these two changes for non-sdv LPT PCHs. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: Workaround incoherence between fences and LLC across multiple CPUsChris Wilson
In order to fully serialize access to the fenced region and the update to the fence register we need to take extreme measures on SNB+, and manually flush writes to memory prior to writing the fence register in conjunction with the memory barriers placed around the register write. Fixes i-g-t/gem_fence_thrash v2: Bring a bigger gun v3: Switch the bigger gun for heavier bullets (Arjan van de Ven) v4: Remove changes for working generations. v5: Reduce to a per-cpu wbinvd() call prior to updating the fences. v6: Rewrite comments to ellide forgotten history. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62191 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jon Bloomfield <jon.bloomfield@intel.com> Tested-by: Jon Bloomfield <jon.bloomfield@intel.com> (v2) Cc: stable@vger.kernel.org Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: tune down Y tiling scanout warningDaniel Vetter
Userspace can easily hit this and does since Ville added a new evil igt testcase in: commit 069e35e0fc3785faa562adcfd2dd7bbed4cb1dea Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Date: Mon Mar 4 15:34:06 2013 +0200 kms_flip: Add flip-vs-bad-tiling test v2: Fix the spelling in the added comment (Chris). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63246 Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: set CB tuning also for the reduce clockDaniel Vetter
Since the ratio is different, we also need to pass in the parameters for the reduced clock. Might or might not reduce flicker for the auto-downclocking on lvds/eDP. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: fix FP CB tuning limits for lvdsDaniel Vetter
Only on IBX should we set the limiting factor to 25 unconditionally for dual-channel mode, on CPT/PPT 25 only applies when the lvds refclock is 100MHz. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: fix lost FP_CB_TUNE setting for pch pllsDaniel Vetter
commit de13a2e3f88a4da8e85063b6de37096795079e41 Author: Paulo Zanoni <paulo.r.zanoni@intel.com> Date: Thu Sep 20 18:36:05 2012 -0300 drm/i915: extract compute_dpll from ironlake_crtc_mode_set missed the subtle adjustment of the FP1 register. Fix this up by passing a pointer around instead of the value. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/i915: Fix SDVO connector and encoder get_hw_state functionsEgbert Eich
The connector associated with the encoder is considered active when the output associtated with this connector is active on the encoder. The encoder itself is considered active when either there is an active output on it or the respective SDVO channel is active. Having active outputs when the SDVO channel is inactive seems to be inconsistent: such states can be found when intel_modeset_setup_hw_state() collects the hardware state set by the BIOS. This inconsistency will be fixed in intel_sanitize_crtc() (when intel_crtc_update_dpms() is called), this however only happens when the encoder is associated with a crtc. This patch also reverts: commit bd6946e87a98fea11907b2a47368e13044458a35 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Tue Apr 2 21:30:34 2013 +0200 drm/i915: Fix sdvo connector get_hw_state function Signed-off-by: Egbert Eich <eich@suse.de> Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63031 Cc: stable@vger.kernel.org Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-18drm/qxl: fix build with debugfs turned off.Dave Airlie
Reported-by: Randy Dunlap Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-04-17Merge branch 'gma500-next' of git://github.com/patjak/drm-gma500 into drm-nextDave Airlie
Patrik writes: I haven't had much review or testing on other platforms than Poulsbo but at least the following Cedarview bug has been squashed and no regressions reported: https://bugs.freedesktop.org/show_bug.cgi?id=58527 * 'gma500-next' of git://github.com/patjak/drm-gma500: drm/gma500: Add debugging info to psb_gtt_restore() drm/gma500: Check connector status before restoring sdvo gma500:fix build failure for 3.9-rc5 drm/gma500: Fix hibernation problems on sdvo encoders drm/gma500: Add hooks for hibernation drm/gma500: Activate the gtt rebuild on suspend/resume drm/gma500: Add support for rebuilding the gtt drm/gma500: Change fb name so pm-utils doesn't apply quirks gma500: Make VGA and HDMI connector hotpluggable drm/gma500: Clean up various defines drm/gma500: Remove unnecessary function exposure drm/gma500: Type clock limits directly into array and remove defines drm/gma500: Calculate clock in one function instead of three identical drm/gma500: Remove unused i8xx clock limits gma500: medfield: Fix possible NULL pointer dereference drivers: gpu: drm: gma500: Replaced calls kzalloc & memcpy with kmemdup gma500: remove unused drm_psb_no_fb
2013-04-17Merge branch 'drm-next-3.10' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie
into drm-next Alex writes: This is the initial 3.10 pull request for radeon. The big changes here are UVD support and proper tiling support for SI. The rest is bug fixes. I hope to have another pull request later in the week with some new things we've been working on internally. * 'drm-next-3.10' of git://people.freedesktop.org/~agd5f/linux: (28 commits) drm/radeon: Always flush the VM drm/radeon: re-enable PTE/PDE packet for set_page on cayman/TN drm/radeon: cleanup properly if mmio mapping fails drm/radeon/evergreen+: don't enable HPD interrupts on eDP/LVDS drm/radeon: add si tile mode array query v3 drm/radeon: add ring working query drm/radeon: handle broken disabled rb mask gracefully drm/radeon: add pcie set/get lanes callbacks for newer asics drm/radeon: update r600 set/get pcie lane config drm/radeon/kms: replace *REG32_PCIE_P with *REG32_PCIE_PORT drm/radeon: remove unused blit remnants from si.c drm/radeon: add UVD tiling addr config v2 drm/radeon: init UVD clocks to sane defaults drm/radeon: add set_uvd_clocks callback for r7xx v3 drm/radeon: add set_uvd_clocks callback for SI drm/radeon: add set_uvd_clocks callback for evergreen drm/radeon: add set_uvd_clocks callback for ON/LN/TN (v4) drm/radeon: add radeon_atom_get_clock_dividers helper drm/radeon: add pm callback for setting uvd clocks drm/radeon: UVD bringup v8 ...
2013-04-16drm/radeon: Always flush the VMJerome Glisse
This is slightly cleaned up version of Jerome's patch. There seems to be an issue tracking the last flush of the VM which results in hangs in certain cases when VM is used. For now just flush the VM for every IB. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=62959 https://bugs.freedesktop.org/show_bug.cgi?id=62997 Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-04-16drm/radeon: re-enable PTE/PDE packet for set_page on cayman/TNAlex Deucher
PTE/PDE doesn't support a single update (count = 1). We had previously disabled it since it we were hitting that case which let to hangs. The PTE/PDE packet is much more efficient for VM updates where it can be used. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-17Revert "of/exynos_g2d: Add Bindings for exynos G2D driver"Sachin Kamat
This reverts commit 09495dda6a62c74b13412a63528093910ef80edd. The description is incomplete and the location of this file is incorrect. Based on discussion with the Samsung media and DRM subsystem maintainers, the documentaion of Samsung G2D bindings has been placed at: Documentation/devicetree/bindings/gpu/samsung-g2d.txt Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-04-17drm/exynos: drm_connector: Fix error check conditionSachin Kamat
drm_add_edid_modes() returns 0 upon failure to find any modes. Hence check for 0 and not less than 0. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-04-17drm/exynos: drm_rotator: Fix incorrect usage of IS_ERR_OR_NULLSachin Kamat
Use IS_ERR instead of IS_ERR_OR_NULL on clk_get results. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-04-17drm/exynos: mixer: Fix incorrect usage of IS_ERR_OR_NULLSachin Kamat
Use IS_ERR instead of IS_ERR_OR_NULL on clk_get results. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-04-17drm/exynos: hdmi: Fix incorrect usage of IS_ERR_OR_NULLSachin Kamat
Use IS_ERR instead of IS_ERR_OR_NULL on clk_get results. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-04-17drm/exynos: change the method for getting the interruptVikas Sajjan
Replaces the "platform_get_resource() for IORESOURCE_IRQ" with platform_get_resource_byname(). Both in exynos4 and exynos5, FIMD IP has 3 interrupts in the order: "fifo", "vsync", and "lcd_sys". But The FIMD driver expects the "vsync" interrupt to be mentioned as the 1st parameter in the FIMD DT node. So to meet this expectation of the driver, the FIMD DT node was forced to be made by keeping "vsync" as the 1st paramter. For example in exynos4, the FIMD DT node has interrupt numbers mentioned as <11, 1> <11, 0> <11, 2> keeping "vsync" as the 1st paramter. This patch fixes the above mentioned "hack" of re-ordering of the FIMD interrupt numbers by getting interrupt resource of FIMD by using platform_get_resource_byname(). Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-04-17drm/exynos: enable OF_VIDEOMODE and FB_MODE_HELPERS for exynos drm fimdVikas Sajjan
patch adds "select OF_VIDEOMODE" and "select FB_MODE_HELPERS" when EXYNOS_DRM_FIMD config is selected. Also adds the "OF" dependency. Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-04-17drm/exynos: Add display-timing node parsing using video helper functionVikas Sajjan
Add support for parsing the display-timing node using video helper function. The DT node parsing is done only if 'dev.of_node' exists and the NON-DT logic is still maintained under the 'else' part. Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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