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2025-05-06arm64: dts: mediatek: mt6357: Drop regulator-fixed compatiblesNícolas F. R. A. Prado
Some of the regulators in the MT6357 PMIC dtsi have compatible set to regulator-fixed, even though they don't serve any purpose: all those regulators are handled as a whole by the mt6357-regulator driver. In fact this is the only dtsi in this family of chips where this is the case: mt6359 and mt6358 don't have any such compatibles. A side-effect caused by this is that the DT kselftest, which is supposed to identify nodes with compatibles that can be probed, but haven't, shows these nodes as failures. Remove the useless compatibles to move the dtsi in line with the others in its family and fix the DT kselftest failures. Fixes: 55749bb478f8 ("arm64: dts: mediatek: add mt6357 device-tree") Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20250502-mt6357-regulator-fixed-compatibles-removal-v1-1-a582c16743fe@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-06arm64: dts: rockchip: Enable regulators for Radxa E20CChukun Pan
Enable pwm and fixed regulators for Radxa E20C. The pwm regulator is used to power the CPU and GPU. Note that the LPDDR4 voltage is 1.1V. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250401120020.976343-3-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-06arm64: dts: rockchip: Add pwm nodes for RK3528Chukun Pan
Add pwm nodes for RK3528. The PWM core on RK3528 is the same as RK3328, but the driver does not support interrupts yet. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250401120020.976343-2-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-05arm64: dts: rockchip: Add onboard EEPROM for Radxa E20CYao Zi
Radxa E20C ships an onboard I2C EEPROM for storing production information. Enable it in devicetree. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250417120118.17610-6-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-05arm64: dts: rockchip: Add I2C controllers for RK3528Yao Zi
Describe I2C controllers shipped by RK3528 in devicetree. For I2C-2, I2C-4 and I2C-7 which come with only a set of possible pins, a default pin configuration is included. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250417120118.17610-5-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-05arm64: tegra: tegra210-p2894: Align GPIO hog node name with preferred styleKrzysztof Kozlowski
GPIO hogs device node names can use 'hog' prefix or suffix, but the suffix is preferred. The pattern in DT schema might narrow in the future, so adjust the DTS now. Link: https://lore.kernel.org/r/20250115204603.136997-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-05-05arm64: dts: bcm: Add reference to RPi 2 (2nd rev)Stefan Wahren
This adds a reference to the dts of the Raspberry Pi 2 (2nd rev), so we don't need to maintain the content in arm64. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Link: https://lore.kernel.org/r/20250418143307.59235-4-wahrenst@gmx.net Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-05-05arm64: dts: rockchip: add RK3576 RNG nodeNicolas Frattaroli
The RK3576 has a hardware random number generator IP built into the SoC. Add it to the SoC's .dtsi, now that there's a binding and driver for it. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250430-rk3576-hwrng-v1-3-480c15b5843e@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-05arm64: dts: amlogic: Add A5 Reset ControllerZelong Dong
Add the device node and related header file for Amlogic A5 reset controller. Signed-off-by: Zelong Dong <zelong.dong@amlogic.com> Link: https://lore.kernel.org/r/20240918074211.8067-4-zelong.dong@amlogic.com Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Kelvin Zhang <kelvin.zhang@amlogic.com> Link: https://lore.kernel.org/r/20250411-a4-a5-reset-v6-3-89963278c686@amlogic.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-05-05arm64: dts: amlogic: Add A4 Reset ControllerZelong Dong
Add the device node and related header file for Amlogic A4 reset controller. Signed-off-by: Zelong Dong <zelong.dong@amlogic.com> Link: https://lore.kernel.org/r/20240918074211.8067-3-zelong.dong@amlogic.com Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Kelvin Zhang <kelvin.zhang@amlogic.com> Link: https://lore.kernel.org/r/20250411-a4-a5-reset-v6-2-89963278c686@amlogic.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-05-05arm64: dts: amlogic: dreambox: fix missing clkc_audio nodeChristian Hewitt
Add the clkc_audio node to fix audio support on Dreambox One/Two. Fixes: 83a6f4c62cb1 ("arm64: dts: meson: add initial support for Dreambox One/Two") CC: stable@vger.kernel.org Suggested-by: Emanuel Strobel <emanuel.strobel@yahoo.com> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20250503084443.3704866-1-christianshewitt@gmail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-05-05arm64: dts: amlogic: add support for xiaomi-aquaman/Mi TV StickFerass El Hafidi
Xiaomi Mi TV Stick is a small Amlogic-based Android TV stick released in 2020. It is known as `xiaomi-aquaman` internally. Specifications: * Amlogic S805Y SoC * Android TV 9, upgradable to Android TV 10 * 8 GB eMMC * 1 GB of RAM * Wi-Fi + Bluetooth The devicetree is based on p241's DT, with some changes to better match the Mi TV Stick: * there is no Ethernet port, no IR, no CVBS connector on the stick * a white LED is present * adjust memory to have 1 GB of RAM available Signed-off-by: Ferass El Hafidi <funderscore@postmarketos.org> Link: https://lore.kernel.org/r/20250502-aquaman-v6-2-f1af347d9709@postmarketos.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-05-05arm64: dts: amlogic: gxl: set i2c bias to pull-upDa Xue
GXL I2C pins need internal pull-up enabled to operate if there is no external resistor. The pull-up is 60kohms per the datasheet. We should set the bias when i2c pinmux is enabled. Signed-off-by: Da Xue <da@libre.computer> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250425203118.1444481-1-da@libre.computer Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-05-05arm64: dts: renesas: r9a09g047e57-smarc: Enable CAN TransceiverBiju Das
Enable TCAN1046V-Q1 CAN Transceiver populated on RZ/G3E SMARC EVK by modelling it as two instances of tcan1042. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250320164121.193857-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-05arm64: dts: renesas: r9a09g047e57-smarc: Enable CANFDBiju Das
Enable CANFD on the RZ/G3E SMARC EVK platform. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250320164121.193857-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-05arm64: dts: renesas: r9a09g047: Add CANFD nodeBiju Das
Add CANFD node to RZ/G3E ("R9A09G047") SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250320164121.193857-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-05arm64: dts: rockchip: Switch to undeprecated qcom,calibration-variant on RK3399Krzysztof Kozlowski
The property qcom,ath10k-calibration-variant was deprecated in favor of recently introduced generic qcom,calibration-variant, common to all Qualcomm Atheros WiFi bindings. Change will affect out of tree users, like other projects, of this DTS. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250501160208.96451-2-krzysztof.kozlowski@linaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-05arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3566-quartz64-bDiederik de Haas
The Quartz64 Model B has a Winbound 25Q64DWZPIG SPI flash chip, identified as 'U13' on the component placement schematic. In the Quartz 64 Model-B Schematic from 20220124 on page 17, we can see that the VCC connector is connected to VCCIO_FLASH and page 4 shows that that in turn is connected to the VCCIO2 domain. That domain uses vcc_1v8 as its power source. This fixes the following warning: spi-nor spi4.0: supply vcc not found, using dummy regulator Signed-off-by: Diederik de Haas <didi.debian@cknow.org> Link: https://lore.kernel.org/r/20250503152917.138648-3-didi.debian@cknow.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-05arm64: dts: rockchip: Add phy-supply to gmac0 on NanoPi R5SDiederik de Haas
According to paragraph "7.16. Power" of the RTL8211F-CG datasheet, gmac0 needs to have a 3.3V power supply. On page 22 of the NanoPi R5S version 2204, that is identified as VCC_GEPHY_3V3 which is connected to the VCC_3V3 power source. This fixes the following warning: rk_gmac-dwmac fe2a0000.ethernet: supply phy not found, using dummy regulator Signed-off-by: Diederik de Haas <didi.debian@cknow.org> Link: https://lore.kernel.org/r/20250503152917.138648-2-didi.debian@cknow.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-03arm64: dts: allwinner: t527: add EMAC0 to Avaota-A1 boardYixun Lan
On Avaota A1 board, the EMAC0 connect to an external RTL8211F-CG PHY, which features a 25MHz crystal, and using PH8 pin as PHY reset. Signed-off-by: Yixun Lan <dlan@gentoo.org> Link: https://patch.msgid.link/20250430-01-sun55i-emac0-v3-5-6fc000bbccbd@gentoo.org Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-05-03arm64: dts: allwinner: a527: add EMAC0 to Radxa A5E boardYixun Lan
On Radxa A5E board, the EMAC0 connect to external Maxio MAE0621A PHY, which features a 25MHz crystal, and using PH8 pin as PHY reset. Tested on A5E board with schematic V1.20. Tested-by: Corentin LABBE <clabbe.montjoie@gmail.com> Signed-off-by: Yixun Lan <dlan@gentoo.org> Link: https://patch.msgid.link/20250430-01-sun55i-emac0-v3-4-6fc000bbccbd@gentoo.org Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-05-03arm64: dts: allwinner: a523: Add EMAC0 ethernet MACYixun Lan
Add EMAC0 ethernet MAC support which found on A523 variant SoCs, including the A527/T527 chips. MAC0 is compatible to the A64 chip which requires an external PHY. This patch only add RGMII pins for now. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin LABBE <clabbe.montjoie@gmail.com> Signed-off-by: Yixun Lan <dlan@gentoo.org> Link: https://patch.msgid.link/20250430-01-sun55i-emac0-v3-3-6fc000bbccbd@gentoo.org Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-05-02arm64: dts: ti: k3-am65-main: Add missing taps to sdhci0Judith Mendez
For am65x, add missing ITAPDLYSEL values for Default Speed and High Speed SDR modes to sdhci0 node according to the device datasheet [0]. [0] https://www.ti.com/lit/gpn/am6548 Fixes: eac99d38f861 ("arm64: dts: ti: k3-am654-main: Update otap-del-sel values") Cc: stable@vger.kernel.org Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Moteen Shah <m-shah@ti.com> Link: https://lore.kernel.org/r/20250429173009.33994-1-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-am62p-j722s-common-main: Set eMMC clock parent to defaultJudith Mendez
Set eMMC clock parents to the defaults which is MAIN_PLL0_HSDIV5_CLKOUT for eMMC. This change is necessary since DM is not implementing the correct procedure to switch PLL clock source for eMMC and MMC CLK mux is not glich-free. As a preventative action, lets switch back to the defaults. Fixes: b5080c7c1f7e ("arm64: dts: ti: k3-am62p: Add nodes for more IPs") Cc: stable@vger.kernel.org Signed-off-by: Judith Mendez <jm@ti.com> Acked-by: Udit Kumar <u-kumar1@ti.com> Acked-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20250429163337.15634-4-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-am62a-main: Set eMMC clock parent to defaultJudith Mendez
Set eMMC clock parents to the defaults which is MAIN_PLL0_HSDIV5_CLKOUT for eMMC. This change is necessary since DM is not implementing the correct procedure to switch PLL clock source for eMMC and MMC CLK mux is not glich-free. As a preventative action, lets switch back to the defaults. Fixes: d3ae4e8d8b6a ("arm64: dts: ti: k3-am62a-main: Add sdhci0 instance") Cc: stable@vger.kernel.org Signed-off-by: Judith Mendez <jm@ti.com> Acked-by: Udit Kumar <u-kumar1@ti.com> Acked-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20250429163337.15634-3-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-am62-main: Set eMMC clock parent to defaultJudith Mendez
Set eMMC clock parents to the defaults which is MAIN_PLL0_HSDIV5_CLKOUT for eMMC. This change is necessary since DM is not implementing the correct procedure to switch PLL clock source for eMMC and MMC CLK mux is not glich-free. As a preventative action, lets switch back to the defaults. Fixes: c37c58fdeb8a ("arm64: dts: ti: k3-am62: Add more peripheral nodes") Cc: stable@vger.kernel.org Signed-off-by: Judith Mendez <jm@ti.com> Acked-by: Udit Kumar <u-kumar1@ti.com> Acked-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20250429163337.15634-2-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: am62p-verdin: Add ivyFrancesco Dolcini
Add support for Verdin AM62P mated with Verdin Ivy carrier board. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p Link: https://www.toradex.com/products/carrier-board/ivy-carrier-board Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20250430102815.149162-7-francesco@dolcini.it Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: am62p-verdin: Add yaviaFrancesco Dolcini
Add support for Verdin AM62P mated with Verdin Yavia carrier board. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p Link: https://www.toradex.com/products/carrier-board/yavia Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20250430102815.149162-6-francesco@dolcini.it Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: am62p-verdin: Add mallowFrancesco Dolcini
Add support for Verdin AM62P mated with Verdin Mallow carrier board. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p Link: https://www.toradex.com/products/carrier-board/mallow-carrier-board Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20250430102815.149162-5-francesco@dolcini.it Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: am62p-verdin: Add dahliaFrancesco Dolcini
Add support for Verdin AM62P mated with Verdin Dahlia carrier board. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p Link: https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20250430102815.149162-4-francesco@dolcini.it Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: Add Toradex Verdin AM62PFrancesco Dolcini
Add support for Toradex Verdin AM62P computer on module which can be used on different carrier boards and for the Toradex Verdin Development Board carrier board. The module consists of an TI AM62P family SoC, a TPS65219 PMIC, a Gigabit Ethernet PHY, up to 8GB of LPDDR4 RAM, an eMMC, a TLA2024 ADC, an I2C EEPROM, an RX8130 RTC, plus an optional Bluetooth/Wi-Fi module. Anything that is not self-contained on the module is disabled by default. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p Link: https://www.toradex.com/products/carrier-board/verdin-development-board-kit Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20250430102815.149162-3-francesco@dolcini.it Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-j784s4-j742s2-evm-common: Enable ACSPCIE0 output for PCIe1Siddharth Vadapalli
The PCIe reference clock required by the PCIe Endpoints connected to the PCIe connector corresponding to the PCIe1 instance of PCIe on J784S4-EVM and J742S2-EVM is driven by the ACSPCIE0 module. Add the device-tree support for enabling the same. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250422123218.3788223-3-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-j784s4-j742s2-main-common: Add ACSPCIE0 nodeSiddharth Vadapalli
The ACSPCIE0 module on TI's J784S4 SoC is capable of driving the reference clock required by the PCIe Endpoint device. It is an alternative to on-board and external reference clock generators. Add the device-tree node for the same. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250422123218.3788223-2-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-j784s4-j742s2-main-common: Switch to 64-bit address space ↵Siddharth Vadapalli
for PCIe0 and PCIe1 The PCIe0 and PCIe1 instances of PCIe in J742S2 and J784S4 SoCs support: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250422120042.3746004-8-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-j722s-main: Switch to 64-bit address space for PCIe0Siddharth Vadapalli
The PCIe0 instance of PCIe in J722S SoC supports: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250422120042.3746004-7-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-j721s2-main: Switch to 64-bit address space for PCIe1Siddharth Vadapalli
The PCIe1 instance of PCIe in J721S2 SoC supports: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250422120042.3746004-6-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-j721e-main: Switch to 64-bit address space for PCIe0 and ↵Siddharth Vadapalli
PCIe1 The PCIe0 and PCIe1 instances of PCIe in J721E SoC support: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250422120042.3746004-5-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-j721e: Add ranges for PCIe0 DAT1 and PCIe1 DAT1Siddharth Vadapalli
The PCIe0 DAT1 and PCIe1 DAT1 are 4 GB address regions in the 64-bit address space of the respective PCIe Controllers. Hence, update the ranges to include them. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250422120042.3746004-4-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-j7200-main: Switch to 64-bit address space for PCIe1Siddharth Vadapalli
The PCIe0 instance of PCIe in J7200 SoC supports: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250422120042.3746004-3-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-am64-main: Switch to 64-bit address space for PCIe0Siddharth Vadapalli
The PCIe0 instance of PCIe in AM64 SoC supports: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250422120042.3746004-2-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-am6*: Remove disable-wp for eMMCJudith Mendez
Remove disable-wp flag for eMMC nodes since this flag is only applicable to SD according to the binding doc (mmc/mmc-controller-common.yaml). For eMMC, this flag should be ignored but lets remove anyways to cleanup sdhci nodes. Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Moteen Shah <m-shah@ti.com> Link: https://lore.kernel.org/r/20250429151454.4160506-4-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-am62*: Add non-removable flag for eMMCJudith Mendez
EMMC device is non-removable so add 'non-removable' DT property to avoid having to redetect the eMMC after suspend/resume. Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250429151454.4160506-3-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-am6*: Add boot phase flag to support MMC bootJudith Mendez
The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. For eMMC and SD boot modes, voltage regulator nodes, io-expander nodes, gpio nodes, and MMC nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot and eMMC boot. Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Moteen Shah <m-shah@ti.com> Link: https://lore.kernel.org/r/20250429151454.4160506-2-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-01arm64: dts: rockchip: fix usb-c port functionality on rk3588-nanopc-t6John Clark
The USB-C port on the NanoPC-T6 was not providing VBUS (vbus5v0_typec regulator disabled, gpio-58 out lo) due to misconfiguration. The original setup with regulator-always-on and regulator-boot-on forced the port on, masking the issue, but removing these properties revealed that the fusb302 driver was not enabling the regulator dynamically. Changes: - Removed regulator-always-on and regulator-boot-on from vbus5v0_typec and vbus5v0_usb to allow driver control. - Changed power-role from "source" to "dual" in the usb-c-connector to support OTG functionality. - Added pd-revision = /bits/ 8 <0x2 0x0 0x1 0x2> to the FUSB302MPX node to specify USB Power Delivery (PD) Revision 2.0, Version 1.2, ensuring the driver correctly advertises PD capabilities and negotiates power roles (source/sink). - Added op-sink-microwatt and sink-pdos for proper sink mode configuration (1W min, 15W max). - Added typec-power-opmode = "1.5A" to enable 1.5A fallback for non-PD USB-C devices, aligning with the 5V/2A hardware limit. - Set try-power-role to "source" to prioritize VBUS enablement. - Adjusted usb_host0_xhci dr_mode from "host" to "otg" and added usb-role-switch for dual-role support. Testing: - Verified VBUS (5V) delivery to a sink device (USB thumb drive). - Confirmed USB host mode with lsusb detecting connected devices. - Validated USB device mode with adb devices when connected to a PC. - Tested dual-role (OTG) functionality with try-power-role set to "source" and "sink"; "source" prioritizes faster VBUS activation. - Validated functionality with a mobile device, including USB Power Delivery, file transfer, USB tethering, MIDI, and image transfer. - Tested USB-C Ethernet adapter compatibility in host mode. - Tested USB-C hub compatibility in host mode. Signed-off-by: John Clark <inindev@gmail.com> Link: https://lore.kernel.org/r/20250422210345.196050-1-inindev@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-01arm64: dts: exynos: add initial support for Samsung Galaxy J6Kaustabh Chakraborty
Add initial devicetree support for Samsung Galaxy J6 (codename: j6lte), an Exynos7870 device. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Link: https://lore.kernel.org/r/20250501-exynos7870-v7-5-bb579a27e5eb@disroot.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-05-01arm64: dts: exynos: add initial support for Samsung Galaxy A2 CoreKaustabh Chakraborty
Add initial devicetree support for Samsung Galaxy A2 Core (codename: a2corelte), an Exynos7870 device. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Link: https://lore.kernel.org/r/20250501-exynos7870-v7-4-bb579a27e5eb@disroot.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-05-01arm64: dts: exynos: add initial support for Samsung Galaxy J7 PrimeKaustabh Chakraborty
Add initial devicetree support for Samsung Galaxy J7 Prime (codename: on7xelte), an Exynos7870 device. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Link: https://lore.kernel.org/r/20250501-exynos7870-v7-3-bb579a27e5eb@disroot.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-05-01arm64: dts: exynos: add initial devicetree support for exynos7870Kaustabh Chakraborty
Exynos7870 is an arm64 SoC manufactured by Samsung and announced in 2016. It is present in multiple mid-range Samsung phones and tablets. Add basic devicetree support for the SoC, which includes CMUs, pin controllers, I2C, UART, DW-MMC, and USB-DRD. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Link: https://lore.kernel.org/r/20250501-exynos7870-v7-2-bb579a27e5eb@disroot.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-05-01arm64: dts: rockchip: Enable bluetooth of AP6611s on OrangePI5 Max/UltraJimmy Hon
Orange Pi 5 Max and Ultra has onboard AP6611s with Bluetooth 5.3 connected via UART7. The chip reports as: [ 3.747864] Bluetooth: hci0: BCM: chip id 3 [ 3.750021] Bluetooth: hci0: BCM: features 0x0f [ 3.775923] Bluetooth: hci0: SYN43711A0 [ 3.775930] Bluetooth: hci0: BCM (001.001.030) build 0000 Signed-off-by: Jimmy Hon <honyuenkwun@gmail.com> Link: https://lore.kernel.org/r/20250427182019.1862-1-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-01arm64: dts: apple: Add PMIC NVMEMHector Martin
Add device tree entries for NVMEM cells present on the PMIC Signed-off-by: Hector Martin <marcan@marcan.st> Reviewed-by: Nick Chan <towinchenmi@gmail.com> Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Co-developed-by: Sasha Finkelstein <fnkl.kernel@gmail.com> Signed-off-by: Sasha Finkelstein <fnkl.kernel@gmail.com> Reviewed-by: Neal Gompa <neal@gompa.dev> Link: https://lore.kernel.org/r/20250423-spmi-nvmem-v3-3-2985aa722ddc@gmail.com Signed-off-by: Sven Peter <sven@svenpeter.dev>
generated by cgit (git 2.34.1) at 2025-07-19 17:10:31 +0000