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2025-01-08arm64/sysreg: Update ID_AA64SMFR0_EL1 to DDI0601 2024-12Mark Brown
DDI0601 2024-12 introduces SME 2.2 as well as a few new optional features, update sysreg to reflect the changes in ID_AA64SMFR0_EL1 enumerating them. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20250107-arm64-2024-dpisa-v5-2-7578da51fc3d@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2025-01-08arm64: Filter out SVE hwcaps when FEAT_SVE isn't implementedMarc Zyngier
The hwcaps code that exposes SVE features to userspace only considers ID_AA64ZFR0_EL1, while this is only valid when ID_AA64PFR0_EL1.SVE advertises that SVE is actually supported. The expectations are that when ID_AA64PFR0_EL1.SVE is 0, the ID_AA64ZFR0_EL1 register is also 0. So far, so good. Things become a bit more interesting if the HW implements SME. In this case, a few ID_AA64ZFR0_EL1 fields indicate *SME* features. And these fields overlap with their SVE interpretations. But the architecture says that the SME and SVE feature sets must match, so we're still hunky-dory. This goes wrong if the HW implements SME, but not SVE. In this case, we end-up advertising some SVE features to userspace, even if the HW has none. That's because we never consider whether SVE is actually implemented. Oh well. Fix it by restricting all SVE capabilities to ID_AA64PFR0_EL1.SVE being non-zero. The HWCAPS documentation is amended to reflect the actually checks performed by the kernel. Fixes: 06a916feca2b ("arm64: Expose SVE2 features for userspace") Reported-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: stable@vger.kernel.org Reviewed-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20250107-arm64-2024-dpisa-v5-1-7578da51fc3d@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2025-01-08arm64: dts: rockchip: enable hdmi out audio on wolfvision pf5Michael Riesch
Enable HDMI out audio on the WolfVision PF5 mainboard. Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20241218-b4-wolfvision-pf5-update-v1-2-1d1959858708@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: rockchip: fix num-channels property of wolfvision pf5 micMichael Riesch
The Rockchip RK3568 PDM block always considers stereo inputs. Therefore, the number of channels must be always an even number, even if a single mono microphone is attached. Fixes: 0be29f76633a ("arm64: dts: rockchip: add wolfvision pf5 mainboard") Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20241218-b4-wolfvision-pf5-update-v1-1-1d1959858708@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: rockchip: Enable the USB 3.0 port on NanoPi R6C/R6SAnton Kirilov
Enable the USB 3.0 port on FriendlyElec NanoPi R6C/R6S boards. Signed-off-by: Anton Kirilov <anton.kirilov@arm.com> Link: https://lore.kernel.org/r/20241219112532.482891-1-anton.kirilov@arm.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: rockchip: Fix the SD card detection on NanoPi R6C/R6SAnton Kirilov
Fix the SD card detection on FriendlyElec NanoPi R6C/R6S boards. Signed-off-by: Anton Kirilov <anton.kirilov@arm.com> Link: https://lore.kernel.org/r/20241219113145.483205-1-anton.kirilov@arm.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: rockchip: Add FRAM MB85RS128TY to rk3568-mecsbcDavid Jander
The board features a Fujitsu MB85RS128TY FRAM chip connected to spi0 CS 0. Add support for the MB85RS128TY to the device tree. Signed-off-by: David Jander <david@protonic.nl> Signed-off-by: Jonas Rebmann <jre@pengutronix.de> Link: https://lore.kernel.org/r/20241219-mb85rs128ty-mecsbc-v1-2-77a0e851ef19@pengutronix.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: rockchip: Remove unused i2c2 node from rk3568-mecsbcDavid Jander
One of the pins of i2c2 is actually in use as chip select 0 for spi0. The chip select 0 is used for an FRAM chip, which will be added in the next patch. Remove the i2c2 node from the rk3568-mecsbc device tree. Signed-off-by: David Jander <david@protonic.nl> Signed-off-by: Jonas Rebmann <jre@pengutronix.de> Link: https://lore.kernel.org/r/20241219-mb85rs128ty-mecsbc-v1-1-77a0e851ef19@pengutronix.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: rockchip: Fix PCIe3 handling for Edgeble-6TOPS ModulesJagan Teki
The Edgeble 6TOPS modules has configured the PCIe3.0 with - 2 lanes on Port1 of pcie3x2 controller for M.2 M-Key - 2 lanes on Port0 of pcie3x4 controller for B and E-Key The, current DT uses opposite controller nodes that indeed uses incorrect reset, regulator nodes. The configuration also uses refclk oscillator that need to enable explicitly in DT to avoid the probe hang on while reading DBI. So, this patch fixes all these essential issues and make this PCIe work properly. Issues fixed are, - Fix the associate controller nodes for M and B, E-Key - Fix the reset gpio handlings - Fix the regulator handlings and naming convensions - Support pcie_refclk oscillator Fixes: 92eaee21abbd ("arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 B-Key, E-Key") Fixes: 5d85d4c7e03b ("arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 M-Key") Reported-by: Mitchell Ma <machuang@radxa.com> Co-developed-by: Mitchell Ma <machuang@radxa.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20241221151758.345257-1-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: rockchip: Add Radxa E52CFUKAUMI Naoki
Radxa E52C[1] is a compact network computer based on the Rockchip RK3582 SoC: - Dual Cortex-A76 and quad Cortex-A55 CPU - 5TOPS NPU - 2GB/4GB/8GB LPDDR4 RAM - 16GB/32GB/64GB on-board eMMC - microSD card slot - USB 3.0 Type-A HOST port - USB Type-C debug port - USB Type-C power port (5V only) - 2x 2.5GbE ports [1] https://radxa.com/products/network-computer/e52c Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Link: https://lore.kernel.org/r/20241226024630.13702-3-naoki@radxa.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: rockchip: Add BigTreeTech CB2 and Pi2Ivan Sergeev
BigTreeTech CB2 and Pi2 share a lot of hardware configuration, so a common dtsi file was used to define common nodes and properties. This is similar to how BigTreeTech CB1 and Pi are implemented. Signed-off-by: Ivan Sergeev <ivan8215145640@gmail.com> Link: https://lore.kernel.org/r/20250106-bigtreetech-cb2-v7-2-565567e2c0a4@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: kvm: Introduce nvhe stack size constantsKalesh Singh
Refactor nvhe stack code to use NVHE_STACK_SIZE/SHIFT constants, instead of directly using PAGE_SIZE/SHIFT. This makes the code a bit easier to read, without introducing any functional changes. Cc: Marc Zyngier <maz@kernel.org> Cc: Mark Brown <broonie@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will@kernel.org> Signed-off-by: Kalesh Singh <kaleshsingh@google.com> Link: https://lore.kernel.org/r/20241112003336.1375584-1-kaleshsingh@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-08KVM: arm64: Fix nVHE stacktrace VA bits maskVincent Donnefort
The hypervisor VA space size depends on both the ID map's (IDMAP_VA_BITS) and the kernel stage-1 (VA_BITS). However, the hypervisor stacktrace decoding is solely relying on VA_BITS. This is especially an issue when VA_BITS < IDMAP_VA_BITS (i.e. VA_BITS is 39-bit): the hypervisor may have addresses bigger than the stacktrace is masking. Align this mask with hyp_va_bits. Signed-off-by: Vincent Donnefort <vdonnefort@google.com> Link: https://lore.kernel.org/r/20250107112821.416591-1-vdonnefort@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-08arm64: dts: rockchip: Enable USB 3.0 ports on orangepi-5-plusChen-Yu Tsai
The Orange Pi 5 Plus has its first USB 3.0 interface on the SoC wired directly to the USB type C port next to the MASKROM button, and the second interface wired to a USB 3.0 hub which in turn is connected to the USB 3.0 host ports on the board, as well as the USB 2.0 connection on the M.2 E-key slot. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Ondrej Jirman <megi@xff.cz> Link: https://lore.kernel.org/r/20241220161240.109253-1-wens@kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: rockchip: Add H96 Max V58 TV Box based on RK3588 SoCAlexey Charkov
H96 Max V58 is a compact Rockchip RK3588 based device that ships with Android and is meant for use as a TV connected media box. Its hardware includes: - Rockchip RK3588 SoC with a small aluminium heatsink - 4GB or 8GB LPDDR4 RAM - 32GB or 64GB eMMC 5.1 storage (HS400) - Onboard AP6275P wireless module providing 802.11ax 2x2 MIMO WiFi over PCIe connection and Bluetooth 5.3 over UART with two external detachable antennas - 1x GbE using the onboard GMAC and an RTL8211F PHY - 1x USB 2.0 Type-A (also serves as the Maskrom port) - 1x USB 3.0 Type-A - 1x HDMI 2.1 output - 1x optical SPDIF output - LED line display ("88:88" digits plus icons) driven by an FD6551 IC connected over bitbanged I2C (not yet enabled here) - GPIO connected CIR receiver - Single Rockchip RK806-1 PMIC - 12x onboard ambient LEDs lighting up the bottom of the device - 5v DCIN using a standard round 5.5mm connector Signed-off-by: Alexey Charkov <alchark@gmail.com> Link: https://lore.kernel.org/r/20250108-rk3588-h96-max-v58-v2-3-522301b905d6@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: rockchip: Add rk3576 evb1 boardKever Yang
RK3576 EVB1 board features: - Rockchip RK3576 - PMIC: RK806-2x2pcs+DiscretePower - RAM: LPDDR4/4x 2pcsx 32bit - ROM: eMMC5.1 + UFS - LAN x 2 - HDMI TX - SD card slot - PCIe2 slot Add support for pmic, eMMC, SD-card, ADC-KEY, PCIE and GMAC. NOTE: The board has a hardware mux design for - PCIe slot(pcie1) - USB3 host(usb_drd1_dwc3) and default state is switch to USB3. To enable PCIe slot: - hardware: Switch the mux to PCIe side; - dts: disable usb_drd1_dwc3 and enable pcie1; Signed-off-by: Liang Chen <cl@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Link: https://lore.kernel.org/r/20250107074911.550057-8-kever.yang@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08KVM: arm64: Fix FEAT_MTE in pKVMVladimir Murzin
Make sure we do not trap access to Allocation Tags. Fixes: b56680de9c64 ("KVM: arm64: Initialize trap register values in hyp in pKVM") Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Reviewed-by: Oliver Upton <oliver.upton@linux.dev> Reviewed-by: Fuad Tabba <tabba@google.com> Link: https://lore.kernel.org/r/20250106112421.65355-1-vladimir.murzin@arm.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-08arm64: dts: rockchip: add usb related nodes for rk3576Frank Wang
This adds USB and USB-PHY related nodes for RK3576 SoC. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Link: https://lore.kernel.org/r/20250107074911.550057-5-kever.yang@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: rockchip: Add rk3576 naneng combphy nodesKever Yang
rk3576 has two naneng combo phys: - combophy0 is used for one of pcie and sata; - combophy1 is used for one of pcie, sata and usb3; Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Link: https://lore.kernel.org/r/20250107074911.550057-2-kever.yang@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-08arm64: dts: marvell: drop additional phy-names for sataFrank Wunderlich
Commit facbe7092f8a ("arm64: dts: marvell: Drop undocumented SATA phy names") drops some phy-names from devicetrees but misses some. Drop them too. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-01-08arm64: dts: marvell: only enable complete sata nodesFrank Wunderlich
The ahci-platform binding requires phys/target-supply property. After converting the binding to yaml the following files reporting "'anyOf' conditional failed" on sata@540000: sata-port@0 armada-7040-db.dts armada-8040-clearfog-gt-8k.dts armada-8040-mcbin.dts armada-8040-mcbin-singleshot.dts cn9130-db.dts cn9130-db-B.dts cn9131-db.dts cn9131-db-B.dts cn9132-db.dts cn9132-db-B.dts the following files reporting 'anyOf' conditional failed on sata@540000: sata-port@1 cn9132-db.dts cn9132-db-B.dts cn9130-crb-B.dts 'phys' is a required property 'target-supply' is a required property >From schema: Documentation/devicetree/bindings/ata/ahci-platform.yaml This is caused by defining sata-ports incomplete in armada-cp11x.dtsi and overriding only a subset of ports with the needed phys/target-supply property. Fix this by disabling the node-templates and enabling the needed nodes. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-01-08hyperv: Clean up unnecessary #includesNuno Das Neves
Remove includes of linux/hyperv.h, mshyperv.h, and hyperv-tlfs.h where they are not used. Signed-off-by: Nuno Das Neves <nunodasneves@linux.microsoft.com> Acked-by: Wei Liu <wei.liu@kernel.org> Reviewed-by: Michael Kelley <mhklinux@outlook.com> Reviewed-by: Easwar Hariharan <eahariha@linux.microsoft.com> Link: https://lore.kernel.org/r/1732577084-2122-3-git-send-email-nunodasneves@linux.microsoft.com Signed-off-by: Wei Liu <wei.liu@kernel.org> Message-ID: <1732577084-2122-3-git-send-email-nunodasneves@linux.microsoft.com>
2025-01-08arm64: dts: marvell: cn9131-cf-solidwan: fix cp1 comphy linksJosua Mayer
Marvell CN913x platforms use common phy framework for configuring and linking serdes lanes according to their usage. Each CP (X) features 5 serdes lanes (Y) represented by cpX_comphyY nodes. CN9131 SolidWAN uses CP1 serdes lanes 3 and 5 for eth1 and eth2 of CP1 respectively. Devicetree however wrongly links from these ports to the comphy of CP0. Replace the wrong links to cp0_comphy with cp1_comphy inside cp1_eth1, cp1_eth2. Fixes: 1280840d2030 ("arm64: dts: add description for solidrun cn9131 solidwan board") Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-01-07arm64: dts: qcom: sm8250: Fix interrupt types of camss interruptsVladimir Zapolskiy
Qualcomm IP catalog says that all CAMSS interrupts is edge rising, fix it in the CAMSS device tree node for sm8250 SoC. Fixes: 30325603b910 ("arm64: dts: qcom: sm8250: camss: Add CAMSS block definition") Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20241127122950.885982-7-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: sdm845: Fix interrupt types of camss interruptsVladimir Zapolskiy
Qualcomm IP catalog says that all CAMSS interrupts is edge rising, fix it in the CAMSS device tree node for sdm845 SoC. Fixes: d48a6698a6b7 ("arm64: dts: qcom: sdm845: Add CAMSS ISP node") Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20241127122950.885982-6-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: sc8280xp: Fix interrupt type of camss interruptsVladimir Zapolskiy
Qualcomm IP catalog says that all CAMSS interrupts are edge rising, fix it in the CAMSS device tree node for sc8280xp SoC. Fixes: 5994dd60753e ("arm64: dts: qcom: sc8280xp: camss: Add CAMSS block definition") Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20241127122950.885982-5-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: qcs8300-ride: Enable USB controllersKrishna Kurapati
Enable primary USB controller on QCS8300 Ride platform. The primary USB controller is made "peripheral", as this is intended to be connected to a host for debugging use cases. For using the controller in host mode, changing the dr_mode and adding appropriate pinctrl nodes to provide vbus would be sufficient. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241114055152.1562116-3-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: qcs8300: Add support for usb nodesKrishna Kurapati
Add support for USB controllers on QCS8300. The second controller is only High Speed capable. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241114055152.1562116-2-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: qcs8300: Add support for clock controllersImran Shaik
Add support for GPU, Video, Camera and Display clock controllers on Qualcomm QCS8300 platform. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Link: https://lore.kernel.org/r/20241114-qcs8300-mm-cc-dt-patch-v1-1-7a974508c736@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: sm8450: Add coresight nodesMao Jinlong
Add coresight components on Qualcomm SM8450 Soc. The components include TMC ETF/ETR, ETE, STM, TPDM, CTI. Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> Link: https://lore.kernel.org/r/20250107090031.3319-3-quic_jinlmao@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: defconfig: Enable Qualcomm IPQ CMN PLL clock controllerLuo Jie
The CMN PLL hardware block is available in the Qualcomm IPQ SoC such as IPQ9574 and IPQ5332. It provides fixed rate output clocks to Ethernet related hardware blocks such as external Ethernet PHY or switch. This driver is initially being enabled for IPQ9574. All boards based on IPQ9574 SoC will require to include this driver in the build. This CMN PLL hardware block does not provide any other specific function on the IPQ SoC other than enabling output clocks to Ethernet related devices. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-3-c89fb4d4849d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: sa8775p: Fix the size of 'addr_space' regionsManivannan Sadhasivam
For both the controller instances, size of the 'addr_space' region should be 0x1fe00000 as per the hardware memory layout. Otherwise, endpoint drivers cannot request even reasonable BAR size of 1MB. Cc: stable@vger.kernel.org # 6.11 Fixes: c5f5de8434ec ("arm64: dts: qcom: sa8775p: Add ep pcie1 controller node") Fixes: 1924f5518224 ("arm64: dts: qcom: sa8775p: Add ep pcie0 controller node") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20241231130224.38206-2-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: qcs615-ride: Enable UFS nodeSayali Lokhande
Enable UFS on the Qualcomm QCS615 Ride platform. Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Co-developed-by: Xin Liu <quic_liuxin@quicinc.com> Signed-off-by: Xin Liu <quic_liuxin@quicinc.com> Link: https://lore.kernel.org/r/20241216095439.531357-4-quic_liuxin@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: qcs615: add UFS nodeSayali Lokhande
Add the UFS Host Controller node and its PHY for QCS615 SoC. Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Co-developed-by: Xin Liu <quic_liuxin@quicinc.com> Signed-off-by: Xin Liu <quic_liuxin@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241216095439.531357-3-quic_liuxin@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: ipq5424: Add USB controller and phy nodesVaradarajan Narayanan
The IPQ5424 SoC has both USB2.0 and USB3.0 controllers. The USB3.0 can connect to either of USB2.0 or USB3.0 phy and operate in the respective mode. Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241118052839.382431-7-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: ipq5424: Add LLCC/system-cache-controllerVaradarajan Narayanan
Add a DT node for Last level cache (aka. system cache) controller which provides control over the last level cache present on IPQ5424 SoCs. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20241121051935.1055222-4-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64/sme: Move storage of reg_smidr to __cpuinfo_store_cpu()Mark Brown
In commit 892f7237b3ff ("arm64: Delay initialisation of cpuinfo_arm64::reg_{zcr,smcr}") we moved access to ZCR, SMCR and SMIDR later in the boot process in order to ensure that we don't attempt to interact with them if SVE or SME is disabled on the command line. Unfortunately when initialising the boot CPU in init_cpu_features() we work on a copy of the struct cpuinfo_arm64 for the boot CPU used only during boot, not the percpu copy used by the sysfs code. The expectation of the feature identification code was that the ID registers would be read in __cpuinfo_store_cpu() and the values not modified by init_cpu_features(). The main reason for the original change was to avoid early accesses to ZCR on practical systems that were seen shipping with SVE reported in ID registers but traps enabled at EL3 and handled as fatal errors, SME was rolled in due to the similarity with SVE. Since then we have removed the early accesses to ZCR and SMCR in commits: abef0695f9665c3d ("arm64/sve: Remove ZCR pseudo register from cpufeature code") 391208485c3ad50f ("arm64/sve: Remove SMCR pseudo register from cpufeature code") so only the SMIDR_EL1 part of the change remains. Since SMIDR_EL1 is only trapped via FEAT_IDST and not the SME trap it is less likely to be affected by similar issues, and the factors that lead to issues with SVE are less likely to apply to SME. Since we have not yet seen practical SME systems that need to use a command line override (and are only just beginning to see SME systems at all) and the ID register read is much more likely to be safe let's just store SMIDR_EL1 along with all the other ID register reads in __cpuinfo_store_cpu(). This issue wasn't apparent when testing on emulated platforms that do not report values in SMIDR_EL1. Fixes: 892f7237b3ff ("arm64: Delay initialisation of cpuinfo_arm64::reg_{zcr,smcr}") Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20241217-arm64-fix-boot-cpu-smidr-v3-1-7be278a85623@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2025-01-07arm64: mm: Test for pmd_sect() in vmemmap_check_pmd()Zhenhua Huang
Commit 2045a3b8911b ("mm/sparse-vmemmap: generalise vmemmap_populate_hugepages()") introduces the vmemmap_check_pmd() while does not verify if the entry is a section mapping, as is already done for Loongarch & X86. The update includes a check for pmd_sect(). Only if pmd_sect() returns true, further vmemmap population for the addr is skipped. Signed-off-by: Zhenhua Huang <quic_zhenhuah@quicinc.com> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20250102074047.674156-1-quic_zhenhuah@quicinc.com Signed-off-by: Will Deacon <will@kernel.org>
2025-01-07arm64/mm: Replace open encodings with PXD_TABLE_BITAnshuman Khandual
[pgd|p4d]_bad() helpers have open encodings for their respective table bits which can be replaced with corresponding macros. This makes things clearer, thus improving their readability as well. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Ard Biesheuvel <ardb@kernel.org> Cc: Ryan Roberts <ryan.roberts@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Ryan Roberts <ryan.roberts@arm.com> Reviewed-by: Gavin Shan <gshan@redhat.com> Link: https://lore.kernel.org/r/20250107015529.798319-1-anshuman.khandual@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2025-01-07arm64/mm: Rename pte_mkpresent() as pte_mkvalid()Anshuman Khandual
pte_present() is no longer synonymous with pte_valid() as it also tests for pte_present_invalid() as well. Hence pte_mkpresent() is misleading, because all that does is make an entry mapped, via setting PTE_VALID. Hence rename the helper as pte_mkvalid() which reflects its functionality appropriately. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Ard Biesheuvel <ardb@kernel.org> Cc: Ryan Roberts <ryan.roberts@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20250107023016.829416-1-anshuman.khandual@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2025-01-07arm64: dts: qcom: sm8650: Add coresight nodesYuanfang Zhang
Add coresight components: Funnel, ETE and ETF for SM8650. Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com> Link: https://lore.kernel.org/r/20250107-sm8650-cs-dt-v4-1-2113b18754ea@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: x1e80100: Fix usb_2 controller interruptsAbel Vesa
Back when the CRD support was brought up, the usb_2 controller didn't have anything connected to it in order to test it properly, so it was never enabled. On the Lenovo ThinkPad T14s, the usb_2 controller has the fingerprint controller connected to it. So enabling it, proved that the interrupts lines were wrong from the start. Fix both the pwr_event and the DWC ctrl_irq lines, according to documentation. Fixes: 4af46b7bd66f ("arm64: dts: qcom: x1e80100: Add USB nodes") Cc: stable@vger.kernel.org # 6.9 Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20250107-x1e80100-fix-usb2-controller-irqs-v1-1-4689aa9852a7@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: x1e78100-t14s: Enable fingerprint readerAbel Vesa
On Lenovo ThinkPad T14s, the fingerprint reader placed in the power button is connected via the usb_2 controller. The controller has only a USB 2.0 PHY which is then connected via a NXP PTN3222 eUSB2 repeater, which in turn is connected to the Goodix fingerprint reader. So enable all the usb_2 controller and PHY nodes, set dual-role mode to host and describe the eUSB2 repeater in order to get the fingerprint reader discovered. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20250107-x1e80100-t14-enable-fingerprint-sensor-v1-1-8fd911d39ad1@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: defconfig: Enable basic Qualcomm SM8750 SoC driversKrzysztof Kozlowski
Enable necessary drivers for booting Qualcomm SM8750 based boards like MTP8750 and QRD8750. The clock controller (GCC), interconnect and pinctrl drivers are considered necessary for early boot debugging, e.g. via serial console, thus make them built-in. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250107155452.389154-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: x1e80100: Add coresight nodesJie Gan
Add following coresight components for x1e80100 platform. It includes CTI, dummy sink, dynamic Funnel, Replicator, STM, TPDM, TPDA and TMC ETF. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Yushan Li <quic_yushli@quicinc.com> Signed-off-by: Jie Gan <quic_jiegan@quicinc.com> Link: https://lore.kernel.org/r/20241205054904.535465-1-quic_jiegan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: qcs8300-ride: enable ethernet0Yijie Yang
Enable the SerDes PHY on qcs8300-ride. Add the MDC and MDIO pin functions for ethernet0 on qcs8300-ride. Enable the ethernet port on qcs8300-ride. Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241206-dts_qcs8300-v5-2-422e4fda292d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: qcs8300: add the first 2.5G ethernetYijie Yang
Add the node for the first ethernet interface on qcs8300 platform. Add the internal SGMII/SerDes PHY node as well. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com> Link: https://lore.kernel.org/r/20241206-dts_qcs8300-v5-1-422e4fda292d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64: dts: qcom: qcs8300: Add capacity and DPC propertiesJingyi Wang
The "capacity-dmips-mhz" and "dynamic-power-coefficient" are used to build Energy Model which in turn is used by EAS to take placement decisions. So add it to QCS8300 SoC. Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241206-qcs8300_dpc-v1-1-af2e8e6d3da9@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07arm64/sysreg: Update ID_AA64ISAR2_EL1 to DDI0601 2024-09Mark Brown
DDI0601 2024-09 introduces new features which are enumerated via ID_AA64ISAR2_EL1, update the sysreg file to reflect these updates. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20241211-arm64-2024-dpisa-v4-6-0fd403876df2@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2025-01-07arm64/sysreg: Update ID_AA64ZFR0_EL1 to DDI0601 2024-09Mark Brown
DDI0601 2024-09 introduces SVE 2.2 as well as a few new optional features, update sysreg to reflect the changes in ID_AA64ZFR0_EL1 enumerating them. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20241211-arm64-2024-dpisa-v4-4-0fd403876df2@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
generated by cgit (git 2.34.1) at 2025-07-16 00:47:59 +0000