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2025-01-06arm64: dts: qcom: sm8650: Fix MPSS memory lengthKrzysztof Kozlowski
The address space in MPSS/Modem PAS (Peripheral Authentication Service) remoteproc node should point to the QDSP PUB address space (QDSP6...SS_PUB) which has a length of 0x10000. Value of 0x4040 was copied from older DTS, but it grew since then. This should have no functional impact on Linux users, because PAS loader does not use this address space at all. Fixes: 10e024671295 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Cc: stable@vger.kernel.org Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241213-dts-qcom-cdsp-mpss-base-address-v3-12-2e0036fccd8d@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sm8650: Fix CDSP memory lengthKrzysztof Kozlowski
The address space in CDSP PAS (Peripheral Authentication Service) remoteproc node should point to the QDSP PUB address space (QDSP6...SS_PUB) which has a length of 0x10000. Value of 0x1400000 was copied from older DTS, but it does not look accurate at all. This should have no functional impact on Linux users, because PAS loader does not use this address space at all. Fixes: 10e024671295 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Cc: stable@vger.kernel.org Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241213-dts-qcom-cdsp-mpss-base-address-v3-11-2e0036fccd8d@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sm8650: Fix ADSP memory base and lengthKrzysztof Kozlowski
The address space in ADSP PAS (Peripheral Authentication Service) remoteproc node should point to the QDSP PUB address space (QDSP6...SS_PUB): 0x0680_0000 with length of 0x10000. 0x3000_0000, value used so far, is the main region of CDSP. Downstream DTS uses 0x0300_0000, which is oddly similar to 0x3000_0000, yet quite different and points to unused area. Correct the base address and length, which also moves the node to different place to keep things sorted by unit address. The diff looks big, but only the unit address and "reg" property were changed. This should have no functional impact on Linux users, because PAS loader does not use this address space at all. Fixes: 10e024671295 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Cc: stable@vger.kernel.org Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241213-dts-qcom-cdsp-mpss-base-address-v3-10-2e0036fccd8d@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sm8550: Fix MPSS memory lengthKrzysztof Kozlowski
The address space in MPSS/Modem PAS (Peripheral Authentication Service) remoteproc node should point to the QDSP PUB address space (QDSP6...SS_PUB) which has a length of 0x10000. Value of 0x4040 was copied from older DTS, but it grew since then. This should have no functional impact on Linux users, because PAS loader does not use this address space at all. Fixes: d0c061e366ed ("arm64: dts: qcom: sm8550: add adsp, cdsp & mdss nodes") Cc: stable@vger.kernel.org Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241213-dts-qcom-cdsp-mpss-base-address-v3-9-2e0036fccd8d@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sm8550: Fix CDSP memory lengthKrzysztof Kozlowski
The address space in CDSP PAS (Peripheral Authentication Service) remoteproc node should point to the QDSP PUB address space (QDSP6...SS_PUB) which has a length of 0x10000. Value of 0x1400000 was copied from older DTS, but it does not look accurate at all. This should have no functional impact on Linux users, because PAS loader does not use this address space at all. Fixes: d0c061e366ed ("arm64: dts: qcom: sm8550: add adsp, cdsp & mdss nodes") Cc: stable@vger.kernel.org Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241213-dts-qcom-cdsp-mpss-base-address-v3-8-2e0036fccd8d@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sm8550: Fix ADSP memory base and lengthKrzysztof Kozlowski
The address space in ADSP PAS (Peripheral Authentication Service) remoteproc node should point to the QDSP PUB address space (QDSP6...SS_PUB): 0x0680_0000 with length of 0x10000. 0x3000_0000, value used so far, is the main region of CDSP. Downstream DTS uses 0x0300_0000, which is oddly similar to 0x3000_0000, yet quite different and points to unused area. Correct the base address and length, which also moves the node to different place to keep things sorted by unit address. The diff looks big, but only the unit address and "reg" property were changed. This should have no functional impact on Linux users, because PAS loader does not use this address space at all. Fixes: d0c061e366ed ("arm64: dts: qcom: sm8550: add adsp, cdsp & mdss nodes") Cc: stable@vger.kernel.org Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241213-dts-qcom-cdsp-mpss-base-address-v3-7-2e0036fccd8d@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sm8450: Fix MPSS memory lengthKrzysztof Kozlowski
The address space in MPSS/Modem PAS (Peripheral Authentication Service) remoteproc node should point to the QDSP PUB address space (QDSP6...SS_PUB) which has a length of 0x10000. Value of 0x4040 was copied from older DTS, but it grew since then. This should have no functional impact on Linux users, because PAS loader does not use this address space at all. Fixes: 1172729576fb ("arm64: dts: qcom: sm8450: Add remoteproc enablers and instances") Cc: stable@vger.kernel.org Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241213-dts-qcom-cdsp-mpss-base-address-v3-6-2e0036fccd8d@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sm8450: Fix CDSP memory lengthKrzysztof Kozlowski
The address space in CDSP PAS (Peripheral Authentication Service) remoteproc node should point to the QDSP PUB address space (QDSP6...SS_PUB) which has a length of 0x10000. Value of 0x1400000 was copied from older DTS, but it does not look accurate at all. This should have no functional impact on Linux users, because PAS loader does not use this address space at all. Fixes: 1172729576fb ("arm64: dts: qcom: sm8450: Add remoteproc enablers and instances") Cc: stable@vger.kernel.org Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241213-dts-qcom-cdsp-mpss-base-address-v3-5-2e0036fccd8d@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sm8450: Fix ADSP memory base and lengthKrzysztof Kozlowski
The address space in ADSP PAS (Peripheral Authentication Service) remoteproc node should point to the QDSP PUB address space (QDSP6...SS_PUB): 0x0300_0000 with length of 0x10000, which also matches downstream DTS. 0x3000_0000, value used so far, was in datasheet is the region of CDSP. Correct the base address and length, which also moves the node to different place to keep things sorted by unit address. The diff looks big, but only the unit address and "reg" property were changed. This should have no functional impact on Linux users, because PAS loader does not use this address space at all. Fixes: 1172729576fb ("arm64: dts: qcom: sm8450: Add remoteproc enablers and instances") Cc: stable@vger.kernel.org Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241213-dts-qcom-cdsp-mpss-base-address-v3-4-2e0036fccd8d@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sm8350: Fix MPSS memory lengthKrzysztof Kozlowski
The address space in MPSS/Modem PAS (Peripheral Authentication Service) remoteproc node should point to the QDSP PUB address space (QDSP6...SS_PUB) which has a length of 0x10000. Value of 0x4040 was copied from older DTS, but it grew since then. This should have no functional impact on Linux users, because PAS loader does not use this address space at all. Fixes: 177fcf0aeda2 ("arm64: dts: qcom: sm8350: Add remoteprocs") Cc: stable@vger.kernel.org Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241213-dts-qcom-cdsp-mpss-base-address-v3-3-2e0036fccd8d@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sm8350: Fix CDSP memory base and lengthKrzysztof Kozlowski
The address space in CDSP PAS (Peripheral Authentication Service) remoteproc node should point to the QDSP PUB address space (QDSP6...SS_PUB): 0x0a30_0000 with length of 0x10000. 0x9890_0000, value used so far, was copied from downstream DTS, is in the middle of RAM/DDR space and downstream DTS describes the PIL loader, which is a bit different interface. Datasheet says that one of the main CDSP address spaces is 0x0980_0000, which is oddly similar to 0x9890_0000, but quite different. Assume existing value (thus downstream DTS) is not really describing the intended CDSP PAS region. Correct the base address and length, which also moves the node to different place to keep things sorted by unit address. The diff looks big, but only the unit address and "reg" property were changed. This should have no functional impact on Linux users, because PAS loader does not use this address space at all. Fixes: 177fcf0aeda2 ("arm64: dts: qcom: sm8350: Add remoteprocs") Cc: stable@vger.kernel.org Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241213-dts-qcom-cdsp-mpss-base-address-v3-2-2e0036fccd8d@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sm8350: Fix ADSP memory base and lengthKrzysztof Kozlowski
The address space in ADSP PAS (Peripheral Authentication Service) remoteproc node should point to the QDSP PUB address space (QDSP6...SS_PUB): 0x0300_0000 with length of 0x10000. 0x1730_0000, value used so far, was copied from downstream DTS, is in the middle of unused space and downstream DTS describes the PIL loader, which is a bit different interface. Assume existing value (thus downstream DTS) is not really describing the intended ADSP PAS region. Correct the base address and length, which also moves the node to different place to keep things sorted by unit address. The diff looks big, but only the unit address and "reg" property were changed. This should have no functional impact on Linux users, because PAS loader does not use this address space at all. Fixes: 177fcf0aeda2 ("arm64: dts: qcom: sm8350: Add remoteprocs") Cc: stable@vger.kernel.org Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241213-dts-qcom-cdsp-mpss-base-address-v3-1-2e0036fccd8d@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: qcs615-ride: enable SDHC1 and SDHC2Yuanjie Yang
Enable SDHC1 and SDHC2 on the Qualcomm QCS615 Ride platform. Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com> Link: https://lore.kernel.org/r/20241217101017.2933587-3-quic_yuanjiey@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: qcs615: add SDHC1 and SDHC2Yuanjie Yang
Add SDHC1 and SDHC2 support to the QCS615 Ride platform. Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241217101017.2933587-2-quic_yuanjiey@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sdm670: add camccRichard Acayan
The camera clock controller on SDM670 controls the clocks that drive the camera subsystem. The clocks are the same as on SDM845. Add the camera clock controller for SDM670. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241218231729.270137-11-mailingradian@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: correct gpio-ranges for QCS8300Lijuan Gao
Correct the gpio-ranges for the QCS8300 TLMM pin controller to include GPIOs 0-132 and the UFS_RESET pin for primary UFS memory reset. Fixes: 7be190e4bdd2 ("arm64: dts: qcom: add QCS8300 platform") Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241219-correct_gpio_ranges-v2-6-19af8588dbd0@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: correct gpio-ranges for QCS615Lijuan Gao
Correct the gpio-ranges for the QCS615 TLMM pin controller to include GPIOs 0-122 and the UFS_RESET pin for primary UFS memory reset. Fixes: 8e266654a2fe ("arm64: dts: qcom: add QCS615 platform") Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241219-correct_gpio_ranges-v2-5-19af8588dbd0@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: ipq5332: update TRNG compatibleMd Sadre Alam
RNG hardware versions greater than 3.0 are Truly Random Number Generators (TRNG). In IPQ5332, the RNGblock is a TRNG. This patch corrects the compatible property which correctly describes the hardware without making any functional changes Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> Link: https://lore.kernel.org/r/20241226114500.2623804-5-quic_mdalam@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: ipq9574: update TRNG compatibleMd Sadre Alam
RNG hardware versions greater than 3.0 are Truly Random Number Generators (TRNG). In IPQ9574, the RNGblock is a TRNG. This patch corrects the compatible property which correctly describes the hardware without making any functional changes Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> Link: https://lore.kernel.org/r/20241226114500.2623804-4-quic_mdalam@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: ipq5424: add TRNG nodeMd Sadre Alam
Add TRNG (Truly Random Number Generator) node for ipq5424 Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> Link: https://lore.kernel.org/r/20241226114500.2623804-3-quic_mdalam@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: qcm6490-fairphone-fp5: Enable camera EEPROMsLuca Weiss
Configure the EEPROMs which are found on the different camera sensors on this device. The pull-up regulator for these I2C busses is vreg_l6p, the same supply that powers VCC of all the EEPROMs. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250103-fp5-cam-eeprom-v1-5-88dee1b36f8e@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: qcm6490-fairphone-fp5: Prefix regulator-fixed labelLuca Weiss
Add the common vreg_ prefix to the labels of the regulator-fixed. Also make sure the nodes are sorted alphabetically. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250103-fp5-cam-eeprom-v1-4-88dee1b36f8e@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: ipq5424: configure spi0 node for rdp466Manikanta Mylavarapu
Enable the SPI0 node and configure the associated gpio pins. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Link: https://lore.kernel.org/r/20250103063708.3256467-3-quic_mmanikan@quicinc.com [bjorn: Reorder nodes alphabetically] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: ipq5424: add spi nodesManikanta Mylavarapu
Serial engines 4 and 5 on the IPQ5424 support SPI. Serial engine 4 is exclusively dedicated to SPI, whereas serial engine 5 is firmware based and supports SPI, I2C, and UART. The SPI instance operates on serial engine 4, designated as spi0, and on serial engine 5, designated as spi1. Add both the spi0 and spi1 nodes. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250103063708.3256467-2-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: ipq9574: Update xo_board_clk to use fixed factor clockLuo Jie
xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output clock 48 MHZ (also being the reference clock of CMN PLL) divided 2 by analog block routing channel. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-5-c89fb4d4849d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: ipq9574: Add CMN PLL nodeLuo Jie
The CMN PLL clock controller allows selection of an input clock rate from a defined set of input clock rates. It in-turn supplies fixed rate output clocks to the hardware blocks that provide the ethernet functions such as PPE (Packet Process Engine) and connected switch or PHY, and to GCC. The reference clock of CMN PLL is routed from XO to the CMN PLL through the internal WiFi block. .XO (48 MHZ or 96 MHZ)-->WiFi (multiplier/divider)-->48 MHZ to CMN PLL. The reference input clock from WiFi to CMN PLL is fully controlled by the bootstrap pins which select the XO frequency (48 MHZ or 96 MHZ). Based on this frequency, the divider in the internal Wi-Fi block is automatically configured by hardware (1 for 48 MHZ, 2 for 96 MHZ), to ensure output clock to CMN PLL is 48 MHZ. Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-4-c89fb4d4849d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sm8150-microsoft-surface-duo: fix typos in da7280 propertiesNeil Armstrong
The dlg,const-op-mode & dlg,periodic-op-mode were mis-names with twice the "dlg," prefix, drop one to match the bindings. This fixes: sm8150-microsoft-surface-duo.dtb: da7280@4a: 'dlg,const-op-mode' is a required property from schema $id: http://devicetree.org/schemas/input/dlg,da7280.yaml# m8150-microsoft-surface-duo.dtb: da7280@4a: 'dlg,periodic-op-mode' is a required property from schema $id: http://devicetree.org/schemas/input/dlg,da7280.yaml# sm8150-microsoft-surface-duo.dtb: da7280@4a: 'dlg,dlg,const-op-mode', 'dlg,dlg,periodic-op-mode' do not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/input/dlg,da7280.yaml# With the dlg,da7280.yaml converted from dlg,da7280.txt at [1]. [1] https://lore.kernel.org/all/20241206-topic-misc-da7280-convert-v2-1-1c3539f75604@linaro.org/ Fixes: d1f781db47a8 ("arm64: dts: qcom: add initial device-tree for Microsoft Surface Duo") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241230-topic-misc-dt-fixes-v4-6-1e6880e9dda3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sc7180: fix psci power domain node namesNeil Armstrong
Rename the psci power domain node names to match the bindings. This Fixes: sc7180-acer-aspire1.dts: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241230-topic-misc-dt-fixes-v4-5-1e6880e9dda3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sc7180-trogdor-pompom: rename 5v-choke thermal zoneNeil Armstrong
Rename the 5v-choke thermal zone to satisfy the bindings. This fixes: sc7180-trogdor-pompom-r2-lte.dts: thermal-zones: '5v-choke-thermal' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,10}-thermal$', 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/thermal/thermal-zones.yaml# Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241230-topic-misc-dt-fixes-v4-4-1e6880e9dda3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sc7180-trogdor-quackingstick: add missing avee-supplyNeil Armstrong
The bindings requires the avee-supply, use the same regulator as the avdd (positive voltage) which would also provide the negative voltage by definition. The fixes: sc7180-trogdor-quackingstick-r0.dts: panel@0: 'avee-supply' is a required property from schema $id: http://devicetree.org/schemas/display/panel/boe,tv101wum-nl6.yaml# Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241230-topic-misc-dt-fixes-v4-3-1e6880e9dda3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: remove disabled ov7251 ↵Neil Armstrong
camera The ov7251node has bindings check errors in the endpoint, and the camera node was disabled since the beginning. Even when switching the node to okay, the endpoint description to the csiphy is missing along with the csiphy parameters. Drop the ov7251 camera entirely until it's properly described. This obviously fixes: sdm845-db845c-navigation-mezzanine.dtso: camera@60: port:endpoint:data-lanes: [0, 1] is too long from schema $id: http://devicetree.org/schemas/media/i2c/ovti,ov7251.yaml# Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241230-topic-misc-dt-fixes-v4-2-1e6880e9dda3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: qcm6490-shift-otter: remove invalid orientation-switchNeil Armstrong
The orientation-switch property is not documented in the PHY bindings, remove it. This fixes: qcm6490-shift-otter.dts: phy@88e3000: 'orientation-switch' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/phy/qcom,usb-snps-femto-v2.yaml# Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241230-topic-misc-dt-fixes-v4-1-1e6880e9dda3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sc8180x: Disable USB U1/U2 entryPrashanth K
Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On QCS6490-Rb3Gen2 Vision kit, ADB connection is heavily unstable when U1/U2 is enabled. Often when link enters U2, there is a re- enumeration seen and device is unusable for many use cases. 3. On QCS8300/QCS9100, it is observed that when Link enters U2, when the cable is disconnected and reconnected to host PC in HS, there is no link status change interrupt seen and the plug-in in HS doesn't show up a bus reset and enumeration failure happens. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Prashanth K <quic_prashk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241231081115.3149850-18-quic_prashk@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sc8280xp: Disable USB U1/U2 entryPrashanth K
Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On QCS6490-Rb3Gen2 Vision kit, ADB connection is heavily unstable when U1/U2 is enabled. Often when link enters U2, there is a re- enumeration seen and device is unusable for many use cases. 3. On QCS8300/QCS9100, it is observed that when Link enters U2, when the cable is disconnected and reconnected to host PC in HS, there is no link status change interrupt seen and the plug-in in HS doesn't show up a bus reset and enumeration failure happens. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Prashanth K <quic_prashk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241231081115.3149850-17-quic_prashk@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: qdu1000: Disable USB U1/U2 entryPrashanth K
Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On QCS6490-Rb3Gen2 Vision kit, ADB connection is heavily unstable when U1/U2 is enabled. Often when link enters U2, there is a re- enumeration seen and device is unusable for many use cases. 3. On QCS8300/QCS9100, it is observed that when Link enters U2, when the cable is disconnected and reconnected to host PC in HS, there is no link status change interrupt seen and the plug-in in HS doesn't show up a bus reset and enumeration failure happens. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Prashanth K <quic_prashk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241231081115.3149850-16-quic_prashk@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: x1e80100: Disable USB U1/U2 entryPrashanth K
Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On QCS6490-Rb3Gen2 Vision kit, ADB connection is heavily unstable when U1/U2 is enabled. Often when link enters U2, there is a re- enumeration seen and device is unusable for many use cases. 3. On QCS8300/QCS9100, it is observed that when Link enters U2, when the cable is disconnected and reconnected to host PC in HS, there is no link status change interrupt seen and the plug-in in HS doesn't show up a bus reset and enumeration failure happens. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Prashanth K <quic_prashk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241231081115.3149850-15-quic_prashk@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sc7180: Disable USB U1/U2 entryPrashanth K
Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On QCS6490-Rb3Gen2 Vision kit, ADB connection is heavily unstable when U1/U2 is enabled. Often when link enters U2, there is a re- enumeration seen and device is unusable for many use cases. 3. On QCS8300/QCS9100, it is observed that when Link enters U2, when the cable is disconnected and reconnected to host PC in HS, there is no link status change interrupt seen and the plug-in in HS doesn't show up a bus reset and enumeration failure happens. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Prashanth K <quic_prashk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241231081115.3149850-14-quic_prashk@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: qcs404: Disable USB U1/U2 entryPrashanth K
Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On QCS6490-Rb3Gen2 Vision kit, ADB connection is heavily unstable when U1/U2 is enabled. Often when link enters U2, there is a re- enumeration seen and device is unusable for many use cases. 3. On QCS8300/QCS9100, it is observed that when Link enters U2, when the cable is disconnected and reconnected to host PC in HS, there is no link status change interrupt seen and the plug-in in HS doesn't show up a bus reset and enumeration failure happens. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Prashanth K <quic_prashk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241231081115.3149850-13-quic_prashk@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sdx75: Disable USB U1/U2 entryPrashanth K
Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On older targets like SM8150/SM8250/SM8350, there have been throughput issues seen during tethering use cases. 3. On targets like SDX75, intermittent disconnects were observed with certain cables due to impedence variations. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Prashanth K <quic_prashk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241231081115.3149850-12-quic_prashk@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sdm845: Disable USB U1/U2 entryPrashanth K
Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On older targets like SM8150/SM8250/SM8350, there have been throughput issues seen during tethering use cases. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Prashanth K <quic_prashk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241231081115.3149850-11-quic_prashk@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sdm630: Disable USB U1/U2 entryPrashanth K
Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On older targets like SM8150/SM8250/SM8350, there have been throughput issues seen during tethering use cases. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Prashanth K <quic_prashk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241231081115.3149850-10-quic_prashk@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sa8775p: Disable USB U1/U2 entryKrishna Kurapati
Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On QCS6490-Rb3Gen2 Vision kit, ADB connection is heavily unstable when U1/U2 is enabled. Often when link enters U2, there is a re- enumeration seen and device is unusable for many use cases. 3. On QCS8300/QCS9100, it is observed that when Link enters U2, when the cable is disconnected and reconnected to host PC in HS, there is no link status change interrupt seen and the plug-in in HS doesn't show up a bus reset and enumeration failure happens. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Prashanth K <quic_prashk@quicinc.com> Link: https://lore.kernel.org/r/20241231081115.3149850-9-quic_prashk@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sc7280: Disable USB U1/U2 entryKrishna Kurapati
Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On QCS6490-Rb3Gen2 Vision kit, ADB connection is heavily unstable when U1/U2 is enabled. Often when link enters U2, there is a re- enumeration seen and device is unusable for many use cases. 3. On QCS8300/QCS9100, it is observed that when Link enters U2, when the cable is disconnected and reconnected to host PC in HS, there is no link status change interrupt seen and the plug-in in HS doesn't show up a bus reset and enumeration failure happens. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Signed-off-by: Prashanth K <quic_prashk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241231081115.3149850-8-quic_prashk@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sm6350: Disable USB U1/U2 entryKrishna Kurapati
Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On older targets like SM8150/SM8250/SM8350, there have been throughput issues seen during tethering use cases. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Signed-off-by: Prashanth K <quic_prashk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241231081115.3149850-7-quic_prashk@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sm8250: Disable USB U1/U2 entryKrishna Kurapati
Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On older targets like SM8150/SM8250/SM8350, there have been throughput issues seen during tethering use cases. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Signed-off-by: Prashanth K <quic_prashk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241231081115.3149850-6-quic_prashk@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sm6125: Disable USB U1/U2 entryKrishna Kurapati
Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On older targets like SM8150/SM8250/SM8350, there have been throughput issues seen during tethering use cases. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Signed-off-by: Prashanth K <quic_prashk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241231081115.3149850-5-quic_prashk@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sm8150: Disable USB U1/U2 entryKrishna Kurapati
Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On older targets like SM8150/SM8250/SM8350, there have been throughput issues seen during tethering use cases. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Signed-off-by: Prashanth K <quic_prashk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241231081115.3149850-4-quic_prashk@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sm8450: Disable USB U1/U2 entryKrishna Kurapati
Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On older targets like SM8150/SM8250/SM8350, there have been throughput issues seen during tethering use cases. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Signed-off-by: Prashanth K <quic_prashk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241231081115.3149850-3-quic_prashk@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sm8350: Disable USB U1/U2 entryKrishna Kurapati
Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On older targets like SM8150/SM8250/SM8350, there have been throughput issues seen during tethering use cases. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Signed-off-by: Prashanth K <quic_prashk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241231081115.3149850-2-quic_prashk@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: sm8750: Add MTP and QRD boardsMelody Olvera
Add MTP and QRD dts files for SM8750 describing board clocks, regulators, gpio keys, etc. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241204-sm8750_master_dt-v3-6-4d5a8269950b@quicinc.com [bjorn: Polished subject] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit (git 2.34.1) at 2025-07-18 01:11:16 +0000