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2025-01-06arm64: dts: qcom: sm8750: Add pmic dtsiMelody Olvera
Add pmic dtsi file for SM8750 SoC describing the pmics and their thermal zones. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241204-sm8750_master_dt-v3-5-4d5a8269950b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: Add base SM8750 dtsiMelody Olvera
Add the base dtsi for the SM8750 SoC describing the CPUs, GCC and RPMHCC clock controllers, geni UART, interrupt controller, TLMM, reserved memory, interconnects, and SMMU. Co-developed-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Co-developed-by: Jishnu Prakash <quic_jprakash@quicinc.com> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com> Co-developed-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241204-sm8750_master_dt-v3-4-4d5a8269950b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: Add PMIH0108 PMICMelody Olvera
Add descriptions of PMIH0108 PMIC used on SM8750 platforms. Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241204-sm8750_master_dt-v3-3-4d5a8269950b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: qcom: Add PMD8028 PMICMelody Olvera
Add descriptions of PMD8028 PMIC used on SM8750 platforms. Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241204-sm8750_master_dt-v3-2-4d5a8269950b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06arm64: dts: renesas: white-hawk-csi-dsi: Define CSI-2 data line ordersNiklas Söderlund
The second CSI-2 C-PHY data-lanes have different line orders (BCA) than the two other data-lanes (ABC) for both connected CSI-2 receivers, describe this in the device tree. This has worked in the past as the R-Car CSI-2 driver did not have documentation for the line order configuration, hence magic values were written to the registers for this specific setup. Now the registers involved are documented, the hardware description as well as the driver needs to be updated. Note that the numerical values will be replaced by symbolic values later. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250106104458.3596109-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-06arm64: dts: renesas: r8a779g0: Add VSPX instancesJacopo Mondi
Add device nodes for the VSPX instances on R-Car V4H (R8A779G0) SoC. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Jacopo Mondi <jacopo.mondi+renesas@ideasonboard.com> Link: https://lore.kernel.org/20241220-rcar-v4h-vspx-v4-4-7dc1812585ad@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-06arm64: dts: renesas: r8a779g0: Add FCPVX instancesJacopo Mondi
Add device nodes for the FCPVX instances on R-Car V4H (R8A779G0) SoC. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Jacopo Mondi <jacopo.mondi+renesas@ideasonboard.com> Link: https://lore.kernel.org/20241220-rcar-v4h-vspx-v4-2-7dc1812585ad@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-06arm64: dts: renesas: r9a09g047e57-smarc: Add SCIF pincontrolBiju Das
Add device node for SCIF pincontrol. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/20241216195325.164212-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-06bpf, arm64: Emit A64_{ADD,SUB}_I when possible in emit_{lse,ll_sc}_atomic()Peilin Ye
Currently in emit_{lse,ll_sc}_atomic(), if there is an offset, we add it to the base address by doing e.g.: if (off) { emit_a64_mov_i(1, tmp, off, ctx); emit(A64_ADD(1, tmp, tmp, dst), ctx); [...] As pointed out by Xu, we can use emit_a64_add_i() (added in the previous patch) instead, which tries to combine the above into a single A64_ADD_I or A64_SUB_I when possible. Suggested-by: Xu Kuohai <xukuohai@huaweicloud.com> Signed-off-by: Peilin Ye <yepeilin@google.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Acked-by: Xu Kuohai <xukuohai@huawei.com> Link: https://lore.kernel.org/bpf/9ad3034a62361d91a99af24efa03f48c4c9e13ea.1735868489.git.yepeilin@google.com
2025-01-06bpf, arm64: Factor out emit_a64_add_i()Peilin Ye
As suggested by Xu, factor out emit_a64_add_i() for later use. No functional change. Suggested-by: Xu Kuohai <xukuohai@huaweicloud.com> Signed-off-by: Peilin Ye <yepeilin@google.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Acked-by: Xu Kuohai <xukuohai@huawei.com> Link: https://lore.kernel.org/bpf/fedbaca80e6d8bd5bcba1ac5320dfbbdab14472e.1735868489.git.yepeilin@google.com
2025-01-06bpf, arm64: Simplify if logic in emit_lse_atomic()Peilin Ye
Delete that unnecessary outer if clause. No functional change. Signed-off-by: Peilin Ye <yepeilin@google.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Acked-by: Xu Kuohai <xukuohai@huawei.com> Link: https://lore.kernel.org/bpf/e8520e5503a489e2dea8526077976ae5a0ab1849.1735868489.git.yepeilin@google.com
2025-01-04arm64: dts: allwinner: a64: explicitly assign clock parent for TCON0Vasily Khoruzhick
TCON0 seems to need a different clock parent depending on output type. For RGB it has to be PLL-VIDEO0-2X, while for DSI it has to be PLL-MIPI, so select it explicitly. Video output doesn't work if incorrect clock is assigned. On my Pinebook I manually configured PLL-VIDEO0-2X and PLL-MIPI to the same rate, and while video output works fine with PLL-VIDEO0-2X, it doesn't work at all (as in no picture) with PLL-MIPI. Fixes: ca1170b69968 ("clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux") Reviewed-by: Dragan Simic <dsimic@manjaro.org> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Frank Oltmanns <frank@oltmanns.dev> # on PinePhone Tested-by: Stuart Gathman <stuart@gathman.org> # on OG Pinebook Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Link: https://patch.msgid.link/20250104074035.1611136-4-anarsoul@gmail.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-01-03arm64: dts: renesas: r9a09g047: Add pincontrol nodeBiju Das
Add pincontrol node to RZ/G3E ("R9A09G047") SoC DTSI. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/20241216195325.164212-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-03arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Replace RZG2L macrosBiju Das
Replace RZG2L_* macros with RZV2H_* macros, so that we can define port names in alpha-numeric. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/20241216195325.164212-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-03arm64: dts: rockchip: set hdd led labels on QNAP-TS433Heiko Stuebner
The automatically generated names for the LEDs from color and function do not match nicely for the 4 hdds, so set them manually per the label property to also match the LEDs generated from the MCU. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20241107114712.538976-10-heiko@sntech.de
2025-01-03arm64: dts: rockchip: hook up the MCU on the QNAP TS433Heiko Stuebner
The MCU is an important part of the device functionality. It provides functionality like fan-control, more leds, etc and even more important without it, the NAS-device cannot even fully turned off. Hook up the serial device to its uart and hook into the thermal management to control the fan according to the cpu temperature. While the MCU also provides a temperature sensor for the case, this one is just polled and does not provide functionality for handling trip points in hardware, so a lot of polling would be involved. As the cpu is only cooled passively in these devices, it's temperature rising will indicate the temperature level of the system just earlier. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20241107114712.538976-9-heiko@sntech.de
2025-01-03arm64: dts: rockchip: Fix sdmmc access on rk3308-rock-s0 v1.1 boardsJonas Karlman
BootROM leave GPIO4_D6 configured as SDMMC_PWREN function and DW MCI driver set PRWEN high on MMC_POWER_UP and low on MMC_POWER_OFF. Similarly U-Boot also set PRWEN high before accessing mmc. However, HW revision prior to v1.2 must pull GPIO4_D6 low to access sdmmc. For HW revision v1.2 the state of GPIO4_D6 has no impact. Model an always-on active low fixed regulator using GPIO4_D6 to fix use of sdmmc on older HW revisions of the board. Fixes: adeb5d2a4ba4 ("arm64: dts: rockchip: Add Radxa ROCK S0") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20241119230838.4137130-1-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-02KVM: arm64: Work around x1e's CNTVOFF_EL2 bogosityMarc Zyngier
It appears that on Qualcomm's x1e CPU, CNTVOFF_EL2 doesn't really work, specially with HCR_EL2.E2H=1. A non-zero offset results in a screaming virtual timer interrupt, to the tune of a few 100k interrupts per second on a 4 vcpu VM. This is also evidenced by this CPU's inability to correctly run any of the timer selftests. The only case this doesn't break is when this register is set to 0, which breaks VM migration. When HCR_EL2.E2H=0, the timer seems to behave normally, and does not result in an interrupt storm. As a workaround, use the fact that this CPU implements FEAT_ECV, and trap all accesses to the virtual timer and counter, keeping CNTVOFF_EL2 set to zero, and emulate accesses to CVAL/TVAL/CTL and the counter itself, fixing up the timer to account for the missing offset. And if you think this is disgusting, you'd probably be right. Acked-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20241217142321.763801-12-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-02KVM: arm64: nv: Sanitise CNTHCTL_EL2Marc Zyngier
Inject some sanity in CNTHCTL_EL2, ensuring that we don't handle more than we advertise to the guest. Acked-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20241217142321.763801-11-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-02KVM: arm64: nv: Propagate CNTHCTL_EL2.EL1NV{P,V}CT bitsMarc Zyngier
Allow a guest hypervisor to trap accesses to CNT{P,V}CT_EL02 by propagating these trap bits to the host trap configuration. Acked-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20241217142321.763801-10-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-02KVM: arm64: nv: Add trap routing for CNTHCTL_EL2.EL1{NVPCT,NVVCT,TVT,TVCT}Marc Zyngier
For completeness, fun, and cerebral meltdown, add the virtualisation related traps to the counter and timers. Acked-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20241217142321.763801-9-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-02KVM: arm64: Handle counter access early in non-HYP contextMarc Zyngier
We already deal with CNTPCT_EL0 accesses in non-HYP context. Let's add CNTVCT_EL0 as a good measure. This is also an opportunity to simplify things and make it plain that this code is only for non-HYP context handling. Acked-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20241217142321.763801-8-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-02KVM: arm64: nv: Accelerate EL0 counter accesses from hypervisor contextMarc Zyngier
Similarly to handling the physical timer accesses early when FEAT_ECV causes a trap, we try to handle the physical counter without returning to the general sysreg handling. More surprisingly, we introduce something similar for the virtual counter. Although this isn't necessary yet, it will prove useful on systems that have a broken CNTVOFF_EL2 implementation. Yes, they exist. Acked-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20241217142321.763801-7-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-02KVM: arm64: nv: Accelerate EL0 timer read accesses when FEAT_ECV in useMarc Zyngier
Although FEAT_ECV allows us to correctly emulate the timers, it also reduces performances pretty badly. Mitigate this by emulating the CTL/CVAL register reads in the inner run loop, without returning to the general kernel. Acked-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20241217142321.763801-6-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-02KVM: arm64: nv: Use FEAT_ECV to trap access to EL0 timersMarc Zyngier
Although FEAT_NV2 makes most things fast, it also makes it impossible to correctly emulate the timers, as the sysreg accesses are redirected to memory. FEAT_ECV addresses this by giving a hypervisor the ability to trap the EL02 sysregs as well as the virtual timer. Add the required trap setting to make use of the feature, allowing us to elide the ugly resync in the middle of the run loop. Acked-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20241217142321.763801-5-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-02KVM: arm64: nv: Publish emulated timer interrupt state in the in-memory stateMarc Zyngier
With FEAT_NV2, the EL0 timer state is entirely stored in memory, meaning that the hypervisor can only provide a very poor emulation. The only thing we can really do is to publish the interrupt state in the guest view of CNT{P,V}_CTL_EL0, and defer everything else to the next exit. Only FEAT_ECV will allow us to fix it, at the cost of extra trapping. Suggested-by: Chase Conklin <chase.conklin@arm.com> Suggested-by: Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com> Acked-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20241217142321.763801-4-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-02KVM: arm64: nv: Sync nested timer state with FEAT_NV2Marc Zyngier
Emulating the timers with FEAT_NV2 is a bit odd, as the timers can be reconfigured behind our back without the hypervisor even noticing. In the VHE case, that's an actual regression in the architecture... Co-developed-by: Christoffer Dall <christoffer.dall@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@arm.com> Acked-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20241217142321.763801-3-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-02KVM: arm64: nv: Add handling of EL2-specific timer registersMarc Zyngier
Add the required handling for EL2 and EL02 registers, as well as EL1 registers used in the E2H context. This includes handling the virtual timer accesses when CNTHCTL_EL2.EL1TVT or CNTHCTL_EL2.EL1TVCT are set. Acked-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20241217142321.763801-2-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-02arm64: dts: ti: k3-j7200: Add node to disable loopback connectionAnurag Dutta
CTRLMMR_MCU_SPI1_CTRL register controls if MCU_SPI1 is directly connected to SPI3 in the MAIN Domain (default) or if MCU_SPI1 and SPI3 are independently pinned out. By default, the field SPI1_LINKDIS (Bit 0) is set to 0h. In order to disable the direct connection, the SPI1_LINKDIS (Bit 0) needs to be set to 1h. Model this functionality as a "reg-mux" device and based on the idle-state property, enable/disable the connection bewtween MCU_SPI1 and MAIN_SPI3. The register field description has been referred from J7200 TRM [1] (Table 5-517. CTRLMMR_MCU_SPI1_CTRL Register Field Descriptions). [1] https://www.ti.com/lit/pdf/spruiu1 Signed-off-by: Anurag Dutta <a-dutta@ti.com> Link: https://lore.kernel.org/r/20241127075644.210759-1-a-dutta@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-02arm64: dts: ti: k3-j784s4: Use ti,j7200-padconf compatibleThomas Richard
Like on j7200, pinctrl contexts shall be saved and restored during suspend-to-ram. So use ti,j7200-padconf compatible. Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Link: https://lore.kernel.org/r/20241230-j784s4-s2r-pinctrl-v2-1-35039fafe2ca@bootlin.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-02arm64: dts: ti: k3-am62p-j722s-common-main: Enable USB0 for DFU bootSiddharth Vadapalli
Add the "bootph-all" property to the "usb0" device-tree node. This is required for the USB0 instance of USB to be functional at all stages of USB DFU boot. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20241220054550.153360-1-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-02arm64: dts: ti: k3-am62a: Remove duplicate GICR regBryan Brattlof
The GIC Redistributor control range is mapped twice. Remove the extra entry from the reg range. Fixes: 5fc6b1b62639 ("arm64: dts: ti: Introduce AM62A7 family of SoCs") Reported-by: Bin Liu <b-liu@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20241210-am62-gic-fixup-v1-2-758b4d5b4a0a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-02arm64: dts: ti: k3-am62: Remove duplicate GICR regBryan Brattlof
The GIC Redistributor control register range is mapped twice. Remove the extra entry from the reg range. Fixes: f1d17330a5be ("arm64: dts: ti: Introduce base support for AM62x SoC") Reported-by: Bin Liu <b-liu@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20241210-am62-gic-fixup-v1-1-758b4d5b4a0a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-02arm64: dts: ti: k3-am67a-beagley-ai: Add remote processor nodesAndrew Davis
Add nodes for the R5F and C7x cores on the SoC. This includes the mailbox and memory carveouts used by these remote cores. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20241203174114.94751-2-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-02arm64: dts: ti: k3-am62p: Enable Mailbox nodes at the board levelAndrew Davis
Mailbox nodes defined in the top-level J722s/AM62p SoC dtsi files are incomplete and may not be functional unless they are extended with a chosen interrupt and connection to a remote processor. Disable the Mailbox nodes in the dtsi files and only enable the ones that are actually used on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20241203174114.94751-1-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-02arm64: dts: ti: k3-am625-sk: Remove M4 mailbox node redefinitionAndrew Davis
This node is already defined in the included k3-am62x-sk-common.dtsi. Remove this redefinition. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20241203164031.20211-1-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-02arm64: dts: ti: k3-j722s-evm: Enable support for mcu_i2c0Bhavya Kapoor
Enable support for mcu_i2c0 and add pinmux required to bring out the mcu_i2c0 signals on 40-pin RPi expansion header on the J722S EVM. Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Signed-off-by: Shreyash Sinha <s-sinha@ti.com> Reviewed-by: Prasanth Babu Mantena <p-mantena@ti.com> Link: https://lore.kernel.org/r/20241105091224.23453-1-b-kapoor@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-02arm64: dts: ti: k3-am62x-sk-common: Add bootph-all property in ↵Chintan Vankar
cpsw_mac_syscon node Ethernet boot requires CPSW node to be present starting from R5 SPL stage. Add bootph-all property in CPSW MAC's eFuse node cpsw_mac_syscon to enable this node during SPL stage along with later boot stages so that CPSW port will get static MAC address. Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Chintan Vankar <c-vankar@ti.com> Link: https://lore.kernel.org/r/20241114165331.1279065-1-c-vankar@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-12-30arm64: dts: freescale: imx93-9x9-qsb: enable fsl,ext-reset-output for wdog3Peng Fan
The WDOG_B is connected to external PMIC, so set "fsl,ext-reset-output" to enable triggering PMIC reset. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: freescale: imx93-14x14-evk: enable fsl,ext-reset-output for wdog3Peng Fan
The WDOG_B is connected to external PMIC, so set "fsl,ext-reset-output" to enable triggering PMIC reset. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: freescale: imx93-11x11-evk: enable fsl,ext-reset-output for wdog3Peng Fan
The WDOG_B is connected to external PMIC, so set "fsl,ext-reset-output" to enable triggering PMIC reset. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: imx95-19x19-evk: add ENETC 0 supportWei Fang
Add ENETC 0 (1G ethernet port) support for i.MX95-19x19-EVK board. In addition, because all ENETC instances share MDIO bus, so enable EMDIO at the same time. Signed-off-by: Wei Fang <wei.fang@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: imx95: add NETC related nodesWei Fang
Add NETC related nodes for i.MX95. Signed-off-by: Wei Fang <wei.fang@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: imx8mm-phg: Add LVDS compatible stringFabio Estevam
The imx8mm-phg board has an AUO G084SN05 V9 8.4" 800x600 LVDS panel. Improve the devicetree description by passing the LVDS compatible string to fix the following dt-schema warning: imx8mm-phg.dtb: panel: compatible:0: 'panel-lvds' is not one of ['admatec,9904379', 'auo,b101ew05', 'auo,g084sn05', 'chunghwa,claa070wp03xg','edt,etml0700z9ndha', 'hannstar,hsd101pww2', 'hydis,hv070wx2-1e0', 'jenson,bl-jt60050-01a', 'tbs,a711-panel'] ... Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: exynos8895: Add camera hsi2c nodesIvaylo Ivanov
Add nodes for hsi2c1-4 (CAM0-3), which allows using them. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20241221152803.1663820-1-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-30arm64: dts: exynos990: Add clock management unit nodesIgor Belwon
Add CMU nodes for: - cmu_top: provides clocks for other blocks - cmu_hsi0: provides clocks for usb31 Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20241224-cmu-v3-1-33ca24b2413c@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-30arm64: dts: imx93: add pca9452 supportJoy Zou
Support pca9452 on imx93-14x14-evk. Signed-off-by: Joy Zou <joy.zou@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: imx8mn-bsh-smm-s2/pro: add simple-framebufferDario Binacchi
Add a simple-framebuffer node for U-Boot to further fill and activate. Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: imx93-tqma9352-mba93xxla: enable Open Drain for MDIOMarkus Niebel
The board has a pull-up resistor for MDIO pin per PHY design guide. When MDIO is idle, it needs to be high and open drain is better to be used here for power saving. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: imx93-tqma9352-mba93xxca: enable Open Drain for MDIOMarkus Niebel
The board has a pull-up resistor for MDIO pin per PHY design guide. When MDIO is idle, it needs to be high and open drain is better to be used here for power saving. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit (git 2.34.1) at 2025-07-18 05:58:55 +0000