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2024-12-25arm64: dts: qcom: qcs8300: Add ADSP and CDSP0 fastrpc nodesLing Xu
Add ADSP and CDSP0 fastrpc nodes for QCS8300 platform. Signed-off-by: Ling Xu <quic_lxu5@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241119120635.687936-1-quic_lxu5@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25arm64: dts: qcom: sa8775p: Add CPUs to psci power domainMaulik Shah
Commit 4f79d0deae37 ("arm64: dts: qcom: sa8775p: add CPU idle states") already added cpu and cluster idle-states but have not added CPU devices to psci power domain without which idle states do not get detected. Add CPUs to psci power domain. Fixes: 4f79d0deae37 ("arm64: dts: qcom: sa8775p: add CPU idle states") Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20241112-sa8775p_cpuidle-v1-1-66ff3ba72464@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25arm64: dts: qcom: sdm670-google-sargo: add flash ledsRichard Acayan
The Pixel 3a has two identical flash LEDs. Add them together. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241112024050.669578-9-mailingradian@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25arm64: dts: qcom: pm660l: add flash ledsRichard Acayan
The PM660L has support for QPNP flash LEDs. Add them to the device tree. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Link: https://lore.kernel.org/r/20241112024050.669578-8-mailingradian@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25arm64: dts: qcom: sa8775p: Use a SoC-specific compatible for GPI DMAKonrad Dybcio
The commit adding these nodes did not use a SoC-specific node, fix that to comply with bindings guidelines. Fixes: 34d17ccb5db8 ("arm64: dts: qcom: sa8775p: Add GPI configuration") Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241108-topic-sa8775_dma2-v1-2-1d3b0d08d153@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPUMahadevan
Add devicetree changes to enable MDSS0 display-subsystem its display-controller(DPU) for Qualcomm SA8775P platform. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Mahadevan <quic_mahap@quicinc.com> Link: https://lore.kernel.org/r/20241019-patchv3_1-v5-5-d2fb72c9a845@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25arm64: dts: qcom: sa8775p: Add support for clock controllersTaniya Das
Add support for video, camera, display0 and display1 clock controllers on SA8775P. The dispcc1 will be enabled based on board requirements. Reviewed-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241025-sa8775p-mm-v4-resend-patches-v6-2-329a2cac09ae@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25arm64: dts: qcom: sa8775p: Update sleep_clk frequencyTaniya Das
Fix the sleep_clk frequency is 32000 on SA8775P. Fixes: 603f96d4c9d0 ("arm64: dts: qcom: add initial support for qcom sa8775p-ride") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20241025-sa8775p-mm-v4-resend-patches-v6-1-329a2cac09ae@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25arm64: dts: qcom: qcm6490-idp: Allow UFS regulators load/mode settingRakesh Kota
The UFS driver expects to be able to set load (and by extension, mode) on its supply regulators. Add the necessary properties to make that possible. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rakesh Kota <quic_kotarake@quicinc.com> Link: https://lore.kernel.org/r/20241017122858.3664474-1-quic_kotarake@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25arm64: dts: qcom: msm8996-xiaomi-gemini: Fix LP5562 LED1 reg propertyMarek Vasut
The LP5562 led@1 reg property should likely be set to 1 to match the unit. Fix it. Fixes: 4ac46b3682c5 ("arm64: dts: qcom: msm8996: xiaomi-gemini: Add support for Xiaomi Mi 5") Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241006022012.366601-1-marex@denx.de Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25arm64: dts: qcom: qcs6490-rb3gen2: Configure onboard LEDsKonrad Dybcio
RB3 Gen2 has a trio of LEDs connected to the PM8350C's Light Pulse Generator. Describe them. Use the "red channel" as a panic indicator by default. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> [bjorn: Corrected colors] Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241004-rb3gen2-leds-v1-2-437cdbb4f6c0@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25arm64: dts: qcom: pmk8350: Add more SDAM slicesKonrad Dybcio
The downstream tree described more SDAM slices on the PMIC. Some of them are actually required by other peripherals, whereas other are nice to add for hardware description purposes. Add them in. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241004-rb3gen2-leds-v1-1-437cdbb4f6c0@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25arm64: defconfig: Enable sa8775p clock controllersTaniya Das
Enable the SA8775P video, camera and display clock controllers to enable the video, camera and display functionalities on Qualcomm QCS9100 ride and ride rev3 boards. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241024-defconfig_sa8775p_clock_controllers-v2-1-a9e1cdaed785@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25arm64: dts: qcom: ipq9574: Enable PCIe PHYs and controllersdevi priya
Enable the PCIe controller and PHY nodes corresponding to RDP 433. Signed-off-by: devi priya <quic_devipriy@quicinc.com> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Link: https://lore.kernel.org/r/20240801054803.3015572-4-quic_srichara@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodesdevi priya
Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane Gen3 host whereas PCIe2 & PCIe3 are 2-lane Gen3 host. Signed-off-by: devi priya <quic_devipriy@quicinc.com> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Link: https://lore.kernel.org/r/20240801054803.3015572-3-quic_srichara@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25arm64: dts: qcom: sa8775p: fix the secure device bootup issueJie Gan
The secure device(fused) cannot bootup with TPDM_DCC device. So disable it in DT. Fixes: 6596118ccdcd ("arm64: dts: qcom: Add coresight nodes for SA8775p") Signed-off-by: Jie Gan <quic_jiegan@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241219025216.3463527-1-quic_jiegan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Add lid switchAnthony Ruhier
Add the lid switch for the Lenovo Yoga Slim 7x. Other x1e80100 laptops use the GPIO pin 92 only, however on the Yoga Slim 7x this pin seems to be bridged with the pin 71. By default, the pin 71 is set as output-high, which blocks any event on pin 92. This patch sets the pin 71 as output-disable and sets the LID switch on pin 92. This is aligned with how they're configured on Windows: GPIO 71 | 0xf147000 | in | func0 | hi | pull up | 16 mA GPIO 92 | 0xf15c000 | in | func0 | lo | no pull | 2 mA Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Maya Matuszczyk <maccraft123mc@gmail.com> Signed-off-by: Anthony Ruhier <aruhier@mailbox.org> Link: https://lore.kernel.org/r/20241219-patch-lenovo-yoga-v3-1-9c4a79068141@mailbox.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25arm64: dts: qcom: sm6350: Fix uart1 interconnect pathLuca Weiss
The path MASTER_QUP_0 to SLAVE_EBI_CH0 would be qup-memory path and not qup-config. Since the qup-memory path is not part of the qcom,geni-uart bindings, just replace that path with the correct path for qup-config. Fixes: b179f35b887b ("arm64: dts: qcom: sm6350: add uart1 node") Cc: stable@vger.kernel.org Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241220-sm6350-uart1-icc-v1-1-f4f10fd91adf@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25arm64: dts: qcom: qcs8300: add QCrypto nodesYuvaraj Ranganathan
Add the QCE and Crypto BAM DMA nodes. Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241223110936.3428125-1-quic_yrangana@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-23arm64: dts: mediatek: mt8183-kukui-jacuzzi: Drop pp3300_panel voltage settingsChen-Yu Tsai
The pp3300_panel fixed regulator is just a load switch. It does not have any regulating capabilities. Thus having voltage constraints on it is wrong. Remove the voltage constraints. Fixes: cabc71b08eb5 ("arm64: dts: mt8183: Add kukui-jacuzzi-damu board") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20241030070224.1006331-2-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-23arm64: defconfig: Enable MediaTek DWMACNícolas F. R. A. Prado
Enable the config for the DWMAC MediaTek glue layer to allow usage of the Ethernet controller present on MT8195 and MT8188 SoCs. Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20241216-genio700-configs-eth-sound-v1-2-04a719035d6e@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-23arm64: defconfig: Enable sound for MT8188Nícolas F. R. A. Prado
Enable platform and machine sound drivers for the MT8188 SoC with the MT6359 PMIC codec, as well as the MT8186 SOF driver which is also compatible with MT8188, in order to get working sound on MT8188 SoCs. Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20241216-genio700-configs-eth-sound-v1-1-04a719035d6e@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-23arm64: defconfig: Enable MediaTek STAR Ethernet MACNícolas F. R. A. Prado
Enable CONFIG_NET_VENDOR_MEDIATEK and CONFIG_NET_MEDIATEK_STAR_EMAC in the defconfig to allow usage of the Ethernet controller on the MT8365 SoC. Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20241220-mt8365-eth-config-v1-1-7f3ffae35fd6@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-23arm64: dts: mediatek: Set mediatek,mac-wol on DWMAC node for all boardsNícolas F. R. A. Prado
Due to the mediatek,mac-wol property previously being handled backwards by the dwmac-mediatek driver, its use in the DTs seems to have been inconsistent. Now that the driver has been fixed, correct this description. All the currently upstream boards support MAC WOL, so add the mediatek,mac-wol property to the missing ones. Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20241109-mediatek-mac-wol-noninverted-v2-2-0e264e213878@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-22arm64: dts: exynos: Add initial support for Samsung Galaxy S9 (SM-G960F)Markuss Broks
Samsung Galaxy S9 (SM-G960F), codenamed starlte, is a mobile phone released in 2017. It has 4GB of RAM, 64GB of UFS storage, Exynos9810 SoC and 1440x2960 Super AMOLED display. This initial device tree enables the framebuffer pre-initialised by bootloader and physical buttons of the device, with more support to come in the future. Co-developed-by: Maksym Holovach <nergzd@nergzd723.xyz> Signed-off-by: Maksym Holovach <nergzd@nergzd723.xyz> Signed-off-by: Markuss Broks <markuss.broks@gmail.com> Link: https://lore.kernel.org/r/20241214-exynos9810-v4-2-4e91fbbc2133@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-22arm64: dts: exynos: Add Exynos9810 SoC supportMarkuss Broks
Exynos 9810 is an ARMv8 mobile SoC found in various Samsung devices, such as Samsung Galaxy S9 (starlte), S9 Plus (star2lte), Note 9 (crownlte) and perhaps others. Add minimal support for this SoC, including basic stuff like: - PSCI for bringing up secondary cores - ARMv8 generic timer - GPIO and pinctrl. The firmware coming with the devices based on this SoC is buggy and doesn't configure CNTFRQ_EL0, as required by spec, so it's needed to hardcode the frequency in the timer node. Co-developed-by: Maksym Holovach <nergzd@nergzd723.xyz> Signed-off-by: Maksym Holovach <nergzd@nergzd723.xyz> Signed-off-by: Markuss Broks <markuss.broks@gmail.com> Link: https://lore.kernel.org/r/20241214-exynos9810-v4-1-4e91fbbc2133@gmail.com [krzysztof: Rename and move PMU nodes to proper sorting position] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-22arm64: dts: exynos850-e850-96: Specify reserved secure memory explicitlySam Protsenko
Instead of carving out the secure area in 'memory' node, let's describe it in 'reserved-memory'. That makes it easier to understand both RAM regions and particular secure world memory region. Originally the device tree was created in a way to make sure it was well aligned with the way LittleKernel bootloader modified it. But later it was found the LittleKernel works fine with properly described reserved regions, so it's possible now to define those in a cleaner way. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20241211033027.12985-1-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-22arm64: dts: exynos990: Add a PMU node for the third clusterUmer Uddin
Since we have a PMU compatiable for Samsung's Mongoose cores now, drop the comment that explains the lack of it and define the node. Signed-off-by: Umer Uddin <umer.uddin@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20241214115855.49138-2-umer.uddin@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-22KVM: arm64: nv: Advertise the lack of AArch32 EL0 supportMarc Zyngier
Although we never supported 32bit anywhere in NV, we fail to advertise so for EL0, probably owing to the relative lack of hardware supporting both NV2 and 32bit EL0. Add some sanitising to ID_AA64PFR0_EL1.EL0, and reaffirm that "in 64bit-only we trust". Reported-by: Oliver Upton <oliver.upton@linux.dev> Acked-by: Oliver Upton <oliver.upton@linux.dev> Signed-off-by: Marc Zyngier <maz@kernel.org>
2024-12-21Merge tag 'soc-fixes-6.13-2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC fixes from Arnd Bergmann: "Two more small fixes, correcting the cacheline size on Raspberry Pi 5 and fixing a logic mistake in the microchip mpfs firmware driver" * tag 'soc-fixes-6.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: arm64: dts: broadcom: Fix L2 linesize for Raspberry Pi 5 firmware: microchip: fix UL_IAP lock check in mpfs_auto_update_state()
2024-12-20arm64: dts: qcom: x1e001de-devkit: Enable SD card supportSibi Sankar
The SD card slot found on the X1E001DE Snapdragon Devkit for windows board is controlled by SDC2 instance, so enable it. Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241025123551.3528206-3-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-20arm64: dts: qcom: x1e80100-qcp: Enable SD card supportAbel Vesa
One of the SD card slots found on the X Elite QCP board is controlled by the SDC2. Enable it and describe the board specific resources. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20241212-x1e80100-qcp-sdhc-v4-2-a74c48ee68a3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-20arm64: dts: qcom: x1e80100: Describe the SDHC controllersAbel Vesa
The X Elite platform features two SDHC v5 controllers. Describe the controllers along with the pin configuration in TLMM for the SDC2, since they are hardwired and cannot be muxed to any other function. The SDC4 pin configuration can be muxed to different functions, so leave those to board specific dts. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20241212-x1e80100-qcp-sdhc-v4-1-a74c48ee68a3@linaro.org [bjorn: Replaced 0s with QCOM_ICC_TAG_ALWAYS] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-20arm64: dts: qcom: qcs615: Add CPU and LLCC BWMON supportLijuan Gao
Add CPU and LLCC BWMON nodes and their corresponding opp tables to support bandwidth monitoring on QCS615 SoC. This is necessary to enable power management and optimize system performance from the perspective of dynamically changing LLCC and DDR frequencies. Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241218-add_bwmon_support_for_qcs615-v1-2-680d798a19e5@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-20Merge tag 'arm64-fixes' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 fix from Catalin Marinas: "Fix a sparse warning in the arm64 signal code dealing with the user shadow stack register, GCSPR_EL0" * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64/signal: Silence sparse warning storing GCSPR_EL0
2024-12-21arm64: dts: allwinner: h313: enable DVFS for Tanix TX1Andre Przywara
The merging of the Tanix TX1 .dts file overlapped with the introduction of the CPU OPP .dtsi file, so the TX1 wasn't covered by the patch enabling DVFS for all boards. Add the missing include of that OPP .dtsi file, to allow the box to run at up to 1.3GHz, and enable power saving by using lower OPPs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Link: https://patch.msgid.link/20241215212533.12707-1-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2024-12-20Merge tag 'arm-soc/for-6.13/devicetree-arm64-fixes' of ↵Arnd Bergmann
https://github.com/Broadcom/stblinux into arm/fixes This pull request contains Broadcom ARM64-based SoCs Device Tree fixes for 6.13, please pull the following: - Willow corrects the L2 cache line size on the Raspberry Pi 5 (2712) to the correct value of 64 bytes * tag 'arm-soc/for-6.13/devicetree-arm64-fixes' of https://github.com/Broadcom/stblinux: arm64: dts: broadcom: Fix L2 linesize for Raspberry Pi 5 Link: https://lore.kernel.org/r/20241217190547.868744-1-florian.fainelli@broadcom.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-12-20Merge tag 'renesas-arm-defconfig-for-v6.14-tag1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/defconfig Renesas ARM defconfig updates for v6.14 - Enable Watchdog support for the RZ/V2H(P) SoC and the RZ/V2H EVK board in the ARM64 defconfig, - Refresh shmobile_defconfig for v6.13-rc1, - Enable support for the Renesas RZ/G3E (R9A09G047) SoC in the ARM64 defconfig. * tag 'renesas-arm-defconfig-for-v6.14-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: defconfig: Enable R9A09G047 SoC ARM: shmobile: defconfig: Refresh for v6.13-rc1 arm64: defconfig: Enable Renesas RZ/V2H(P) Watchdog driver Link: https://lore.kernel.org/r/cover.1734689799.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-12-20Merge tag 'renesas-dts-for-v6.14-tag1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt Renesas DTS updates for v6.14 - Add more serial (SCIF), power monitor, ADC, and sound support for the RZ/G3S SoC and the RZ/G3S SMARC SoM and development board, - Add support for the R-Car V4H ES3.0 (R8A779G3) SoC on the White Hawk Single development board, - Add display support for the R-Car V4M SoC and the Gray Hawk Single development board, - Add video capture support for the Gray Hawk Single development board, - Add initial support for the RZ/G3E (R9A09G047) SoC and the RZ/G3E SMARC SoM and Carrier-II EVK development board, - Add support for 5-port MATEnet on the Falcon Ethernet sub-board, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v6.14-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (33 commits) arm64: dts: renesas: r9a09g047: Add I2C nodes arm64: dts: renesas: rzg3s-smarc: Add sound card arm64: dts: renesas: rzg3s-smarc: Enable SSI3 arm64: dts: renesas: Add da7212 audio codec node arm64: dts: renesas: rzg3s-smarc-som: Add versa3 clock generator node arm64: dts: renesas: r9a08g045: Add SSI nodes arm64: dts: renesas: rzg3s-smarc-som: Enable ADC arm64: dts: renesas: r9a08g045: Add ADC node arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM arm64: dts: renesas: r9a09g047: Add OPP table arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC arm64: dts: renesas: falcon-ethernet: Describe PHYs connected on the breakout board arm64: dts: renesas: r8a779a0: Remove address- and size-cells from AVB[1-5] dt-bindings: clock: renesas: Document RZ/G3E SoC CPG dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants arm64: dts: renesas: gray-hawk-single: Add video capture support arm64: dts: renesas: gray-hawk-single: Add DisplayPort support arm64: dts: renesas: r8a779h0: Add display support ... Link: https://lore.kernel.org/r/cover.1734689803.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-12-20Merge tag 'stm32-dt-for-v6.14-1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt STM32 DT for v6.14, round 1 Highlights: ---------- - MPU: - STM32MP13: - Populate all timer counter nodes in Soc file. - Enable counter (timers) on stm32mp135f-dk. - DH core: increase CPU voltage to fit with STM32MP135F datasheet. - STMP32MP15: - Populate all timer counter nodes in Soc file. - Enable counter (timers) on stm32mp15 EV1 and DK boards. - OCTAVO: - LXA-TAC (gen1/2): disable RTC, update aliases and adjust USB gadget. - Add LXA-TAC gen3 based on OSD32MP153x SIP: STMP32MP153, RAM, PMIC. - DH: minor fixes. - STM32MP25: - Enable imx335/CSI/DCMIPP pipeline on stm32mp257f-ev1. - Add I2S, SAI, SPDIFRX supports. - Add and enable COMBOPHY on stm32mp257f-ev1. Combophy is used by PCIe and USB3. * tag 'stm32-dt-for-v6.14-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (23 commits) arm64: dts: st: enable imx335/csi/dcmipp pipeline on stm32mp257f-ev1 arm64: dts: st: add csi & dcmipp node in stm32mp25 ARM: dts: stm32: Swap USART3 and UART8 alias on STM32MP15xx DHCOM SoM ARM: dts: stm32: add counter subnodes on stm32mp157 dk boards ARM: dts: stm32: add counter subnodes on stm32mp157c-ev1 ARM: dts: stm32: add counter subnodes on stm32mp135f-dk ARM: dts: stm32: populate all timer counter nodes on stm32mp15 ARM: dts: stm32: populate all timer counter nodes on stm32mp13 ARM: dts: stm32: lxa-tac: Add support for generation 3 devices ARM: dts: stm32: lxa-tac: move adc and gpio{e,g} to gen{1,2} boards dt-bindings: arm: stm32: add compatible strings for Linux Automation LXA TAC gen 3 ARM: dts: stm32: lxa-tac: adjust USB gadget fifo sizes for multi function ARM: dts: stm32: lxa-tac: extend the alias table ARM: dts: stm32: lxa-tac: disable the real time clock ARM: dts: stm32: Fix IPCC EXTI declaration on stm32mp151 ARM: dts: stm32: Sort M24256E write-lockable page in DH STM32MP13xx DHCOR SoM DT ARM: dts: stm32: Increase CPU core voltage on STM32MP13xx DHCOR SoM ARM: dts: stm32: Deduplicate serial aliases and chosen node for STM32MP15xx DHCOM SoM arm64: dts: st: Enable COMBOPHY on the stm32mp257f-ev1 board arm64: dts: st: Add combophy node on stm32mp251 ... Link: https://lore.kernel.org/r/7ffcca65-3953-413a-bcf3-0702a6b0518b@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-12-21arm64: dts: allwinner: a100: Add syscon nodesCody Eksal
The Allwinner A100 has a system configuration block, denoted as SYS_CFG in the user manual's memory map. It is undocumented in the manual, but a glance at the vendor tree shows this block is similar to its predecessors in the A64 and H6. The A100 also has 3 SRAM blocks: A1, A2, and C. Add all of these to the SoC's device tree. Reviewed-by: Parthiban Nallathambi <parthiban@linumiz.com> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest> Link: https://patch.msgid.link/20241218-a100-syscon-v2-2-dae60b9ce192@epochal.quest Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2024-12-20arm64/signal: Silence sparse warning storing GCSPR_EL0Mark Brown
We are seeing a sparse warning in gcs_restore_signal(): arch/arm64/kernel/signal.c:1054:9: sparse: sparse: cast removes address space '__user' of expression when storing the final GCSPR_EL0 value back into the register, caused by the fact that write_sysreg_s() casts the value it writes to a u64 which sparse sees as discarding the __userness of the pointer. Avoid this by treating the address as an integer, casting to a pointer only when using it to write to userspace. While we're at it also inline gcs_signal_cap_valid() into it's one user and make equivalent updates to gcs_signal_entry(). Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202412082005.OBJ0BbWs-lkp@intel.com/ Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20241214-arm64-gcs-signal-sparse-v3-1-5e8d18fffc0c@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2024-12-20KVM: arm64: Use kvm_vcpu_has_feature() directly for struct kvmFuad Tabba
Now that we have introduced kvm_vcpu_has_feature(), use it in the remaining code that checks for features in struct kvm, instead of using the __vcpu_has_feature() helper. No functional change intended. Suggested-by: Quentin Perret <qperret@google.com> Signed-off-by: Fuad Tabba <tabba@google.com> Link: https://lore.kernel.org/r/20241216105057.579031-18-tabba@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2024-12-20KVM: arm64: Convert the SVE guest vcpu flag to a vm flagFuad Tabba
The vcpu flag GUEST_HAS_SVE is per-vcpu, but it is based on what is now a per-vm feature. Make the flag per-vm. Signed-off-by: Fuad Tabba <tabba@google.com> Link: https://lore.kernel.org/r/20241216105057.579031-17-tabba@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2024-12-20KVM: arm64: Remove PtrAuth guest vcpu flagFuad Tabba
The vcpu flag GUEST_HAS_PTRAUTH is always associated with the vcpu PtrAuth features, which are defined per vm rather than per vcpu. Remove the flag, and replace it with checks for the features instead. Signed-off-by: Fuad Tabba <tabba@google.com> Link: https://lore.kernel.org/r/20241216105057.579031-16-tabba@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2024-12-20KVM: arm64: Fix the value of the CPTR_EL2 RES1 bitmask for nVHEFuad Tabba
Since the introduction of SME, bit 12 in CPTR_EL2 (nVHE) is TSM for trapping SME, instead of RES1, as per ARM ARM DDI 0487K.a, section D23.2.34. Fix the value of CPTR_NVHE_EL2_RES1 to reflect that, and adjust the code that relies on it accordingly. Signed-off-by: Fuad Tabba <tabba@google.com> Link: https://lore.kernel.org/r/20241216105057.579031-15-tabba@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2024-12-20KVM: arm64: Refactor kvm_reset_cptr_el2()Fuad Tabba
Fold kvm_get_reset_cptr_el2() into kvm_reset_cptr_el2(), since it is its only caller. Add a comment to clarify that this function is meant for the host value of cptr_el2. No functional change intended. Signed-off-by: Fuad Tabba <tabba@google.com> Link: https://lore.kernel.org/r/20241216105057.579031-14-tabba@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2024-12-20KVM: arm64: Calculate cptr_el2 traps on activating trapsFuad Tabba
Similar to VHE, calculate the value of cptr_el2 from scratch on activate traps. This removes the need to store cptr_el2 in every vcpu structure. Moreover, some traps, such as whether the guest owns the fp registers, need to be set on every vcpu run. Reported-by: James Clark <james.clark@linaro.org> Fixes: 5294afdbf45a ("KVM: arm64: Exclude FP ownership from kvm_vcpu_arch") Signed-off-by: Fuad Tabba <tabba@google.com> Link: https://lore.kernel.org/r/20241216105057.579031-13-tabba@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2024-12-20KVM: arm64: Remove redundant setting of HCR_EL2 trap bitFuad Tabba
In hVHE mode, HCR_E2H should be set for both protected and non-protected VMs. Since commit b56680de9c64 ("KVM: arm64: Initialize trap register values in hyp in pKVM"), this has been fixed, and the setting of the flag here is redundant. Signed-off-by: Fuad Tabba <tabba@google.com> Link: https://lore.kernel.org/r/20241216105057.579031-12-tabba@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2024-12-20KVM: arm64: Remove fixed_config.h headerFuad Tabba
The few remaining items needed in fixed_config.h are better suited for pkvm.h. Move them there and delete it. No functional change intended. Signed-off-by: Fuad Tabba <tabba@google.com> Link: https://lore.kernel.org/r/20241216105057.579031-11-tabba@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
generated by cgit (git 2.34.1) at 2025-07-18 19:23:48 +0000