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2025-05-09Merge tag 'socfpga_dts_updates_for_v6.15' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt SoCFPGA DTS updates for v6.15 - Updates to dt-bindings - Document Agilex5 NAND daughter board - Convert Stratix10 FPGA Manager to json-schema - Convert Stratix10 Service Layer to json-schema - Add document for Terasic's DE10-nano board - Add support for Agilex5 NAND daughter board - Add basic support for Terasic's DE10-nano board * tag 'socfpga_dts_updates_for_v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: dts: socfpga: agilex: Add dma channel id for spi arm64: dts: socfpga: agilex5: add led and memory nodes arm64: dts: intel: socfpga_agilex: add frequencies to internal oscillators ARM: dts: socfpga: Add basic support for Terrasic's de10-nano dt-bindings: altera: Add compatible for Terasic's DE10-nano arm64: dts: socfpga: agilex5: add qspi flash node dt-bindings: firmware: stratix10: Convert to json-schema dt-bindings: fpga: stratix10: Convert to json-schema arm64: dts: socfpga: agilex5: fix gpio0 address arm64: dts: socfpga: agilex5: add NAND daughter board dt-bindings: intel: document Agilex5 NAND daughter board Link: https://lore.kernel.org/r/20250326121152.1739873-1-dinguyen@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-09arm64: dts: amazon: Fix simple-bus node name schema warningsRob Herring (Arm)
Fix a couple of node name warnings from the schema checks: arch/arm64/boot/dts/amazon/alpine-v2-evp.dt.yaml: io-fabric: $nodename:0: 'io-fabric' does not match '^(bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' arch/arm64/boot/dts/amazon/alpine-v3-evp.dt.yaml: io-fabric: $nodename:0: 'io-fabric' does not match '^(bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250409210255.1541298-1-robh@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-09arm64: dts: rockchip: add Rock 5B+Sebastian Reichel
Add ROCK 5B+, which is an improved version of the ROCK 5B with the following changes: * Memory LPDDR4X -> LPDDR5 * HDMI input connector size * eMMC socket -> onboard * M.2 E-Key is replaced by onboard RTL8852BE WLAN/BT * M.2 M-Key 1x4 lanes is replaced by 2x2 lanes * Added M.2 B-Key for USB connected WWAN modules (untested) * Add second camera port (not yet supported in upstream Linux) * Add dedicated USB-C port for device power (no impact in DT; the existing port has not been changed and the new port is handled by CH224D standalone chip) Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20250508-rock5bp-for-upstream-v2-4-677033cc1ac2@kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-09arm64: dts: rockchip: move rock 5b to include fileSebastian Reichel
Radxa released some more boards, which are based on the original Rock 5B. Move its board description into an include file to avoid unnecessary duplication. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20250508-rock5bp-for-upstream-v2-1-677033cc1ac2@kernel.org Link: https://lore.kernel.org/r/20250508-rock5bp-for-upstream-v2-2-677033cc1ac2@kernel.org [The original submission was split into two elements, renaming the file and then moving some nodes around. This was done to make review easier due to the diff being smaller. This commit is a squash of both of them to facilitate bisectability and was also intended by the original author] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-09arm64: dts: rockchip: Add rk3399-evb-ind boardChaoyi Chen
General feature for rk3399 industry evaluation board: - Rockchip RK3399 - 4GB LPDDR4 - emmc5.1 - SDIO3.0 compatible TF card - 1x HDMI2.0a TX - 1x HDMI1.4b RX with TC358749XBG HDMI to MIPI CSI2 bridge chip - 1x type-c DisplayPort - 3x USB3.0 Host - 1x USB2.0 Host - 1x Ethernet / USB3.0 to Ethernet Tested with HDMI/GPU/USB2.0/USB3.0/TF card/emmc. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> Link: https://lore.kernel.org/r/20250506034347.57-3-kernel@airkyi.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-09arm64: defconfig: Enable Rockchip SAI and ES8328Nicolas Frattaroli
The RK3576 uses Rockchip SAI for audio output. Meanwhile, the Sige5 board, which uses the RK3576 and is supported by mainline, uses an ES8388 codec over I2C with the ES8328 driver implementing support for this codec. Enable both in the defconfig. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250506-rk3576-sai-v4-5-a8b5f5733ceb@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-09arm64: dts: rockchip: Enable HDMI audio on Sige5Nicolas Frattaroli
With the hdmi_sound node added to the base RK3576 SoC tree, we can now enable it on the Sige5 SBC. Do this, and also enable the corresponding SAI6 audio controller node. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250506-rk3576-sai-v4-4-a8b5f5733ceb@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-09arm64: dts: rockchip: Add analog audio on RK3576 Sige5Nicolas Frattaroli
The ArmSoM Sige5 board features an Everest ES8388 codec to provide analog stereo audio output, as well as analog audio input. The codec hangs off the i2c2 bus and responds to address 0x10. It is connected to the SAI1 audio controller of the RK3576, with one SDO (output) lane and one SDI (input) lane. The codec has two sets of outputs. One set, LOUT1/ROUT1, is connected through a set of 22uF non-polarised coupling capacitors to a 3-position connector that appears to be a clone of the JST BM03B-SURS-TF header, and is capable of mating with a JST 03SUR-32S (or JST 03SUR-36L if you prefer lemon-lime) or compatible clone connector. The right headphone output is the one closest to the Type-C DC input connector, the left headphone output is the one in the middle, and the third position, the one closest to the USB3 Type-A host connector, is puzzingly labelled as "HP_GND" in the schematic but is in fact connected to the codecs RIN1 input through a 1uF non-plarised coupling capacitor. LOUT2 and ROUT2 are routed to 1mm test pads T36 and T37 respectively. These are located on the bottom of the board, and do not go through any coupling capacitor. For use as line out, the ES8388 datasheet recommends adding 1uF coupling capacitor if one wishes to use it as a line-level output. There is also a pair of inputs for a stereo microphone, going from two 1mm testpads T34 and T35, which are decoupled with a 100pF capacitor and pulled to 3.3v and ground respectively. These inputs then go through 1uF capacitors each and end up in the LINPUT2 and RINPUT2 pins of the ES8388 codec. The codec's power inputs are routed to receive 3.3V for both its analog and digital inputs, though from different supplies. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250506-rk3576-sai-v4-3-a8b5f5733ceb@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-09arm64: dts: rockchip: Add RK3576 HDMI audioNicolas Frattaroli
The RK3576 SoC now has upstream support for HDMI. Add an HDMI audio node, which uses SAI6 as its audio controller according to downstream. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250506-rk3576-sai-v4-2-a8b5f5733ceb@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-09arm64: dts: rockchip: Add RK3576 SAI nodesNicolas Frattaroli
The RK3576 SoC has 10 SAI controllers in total. Five of them are in the video output power domains, and are used for digital audio output along with the video signal of those, e.g. HDMI audio. The other five, SAI0 through SAI4, are exposed externally. SAI0 and SAI1 are capable of 8-channel audio, whereas SAI2, SAI3 and SAI4 are limited to two channels. These five are in the audio power domain. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250506-rk3576-sai-v4-1-a8b5f5733ceb@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-09arm64: dts: rockchip: Enable SD-card interface on Radxa E20CYao Zi
SD-card is available on Radxa E20C board. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250508234829.27111-4-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-09arm64: dts: rockchip: Add SDMMC/SDIO controllers for RK3528Yao Zi
RK3528 features two SDIO controllers and one SD/MMC controller, describe them in devicetree. Since their sample and drive clocks are located in the VO and VPU GRFs, corresponding syscons are added to make these clocks available. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250508234829.27111-3-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-09Merge tag 'arm64-fixes' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 fix from Catalin Marinas: "Move the arm64_use_ng_mappings variable from the .bss to the .data section as it is accessed very early during boot with the MMU off and before the .bss has been initialised. This could lead to incorrect idmap page table" * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: cpufeature: Move arm64_use_ng_mappings to the .data section to prevent wrong idmap generation
2025-05-09Merge tag 'asahi-soc-fixes-6.15' of https://github.com/AsahiLinux/linux into ↵Arnd Bergmann
arm/fixes Apple SoC fixes for 6.15 This tag contains two small commits since rc1: - Add a .mailmap entry requested by Asahi Lina to better filter her emails - Mark the power domains for the touchbar support introduced with 6.15 as always on since the driver cannot initialize the touchbar from scratch after the domains are powered off (e.g. during suspend). * tag 'asahi-soc-fixes-6.15' of https://github.com/AsahiLinux/linux: arm64: dts: apple: touchbar: Mark ps_dispdfr_be as always-on mailmap: Update email for Asahi Lina Link: https://lore.kernel.org/r/20250423145047.3098-1-sven@svenpeter.dev Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-09Merge tag 'amlogic-fixes-for-v6.15' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into arm/fixes Amlogic Fixes for v6.15: - fix reference to unknown/untested PWM clock on ARM/ARM64 boards - fix missing clkc_audio node on dreambox ARM64 DT * tag 'amlogic-fixes-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux: arm64: dts: amlogic: dreambox: fix missing clkc_audio node arm64: dts: amlogic: g12: fix reference to unknown/untested PWM clock arm64: dts: amlogic: gx: fix reference to unknown/untested PWM clock ARM: dts: amlogic: meson8b: fix reference to unknown/untested PWM clock ARM: dts: amlogic: meson8: fix reference to unknown/untested PWM clock Link: https://lore.kernel.org/r/e9c520a1-b986-49e1-b9b1-67511c187716@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-09Merge tag 'v6.15-rockchip-dtsfixes1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes Removal of operating-points above what the rk3588j soc is rated for, and a number of smaller fixes: Turing RK1 fan can spin down again, fixed pins, pinmuxing and clocks and some devicetree-correctnes improvements. * tag 'v6.15-rockchip-dtsfixes1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: fix Sige5 RTC interrupt pin arm64: dts: rockchip: Assign RT5616 MCLK rate on rk3588-friendlyelec-cm3588 arm64: dts: rockchip: Align wifi node name with bindings in CB2 arm64: dts: rockchip: Fix mmc-pwrseq clock name on rock-pi-4 arm64: dts: rockchip: Use "regulator-fixed" for btreg on px30-engicam for vcc3v3-btreg arm64: dts: rockchip: Add pinmuxing for eMMC on QNAP TS433 arm64: dts: rockchip: Remove overdrive-mode OPPs from RK3588J SoC dtsi arm64: dts: rockchip: Allow Turing RK1 cooling fan to spin down Link: https://lore.kernel.org/r/2923598.88bMQJbFj6@diego Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-09arm64: dts: freescale: Add PHYTEC phyBOARD-Nash-i.MX93 supportPrimoz Fiser
Add initial support for PHYTEC phyBOARD-Nash-i.MX93 board [1] based on the PHYTEC phyCORE-i.MX93 SoM (System-on-Module) [2]. Supported board features: * ADC * CAN * Ethernet * EEPROM * RTC * RS-232/RS-485 * SD-card * TPM 2.0 * USB For more details see the product pages for the development kit and the SoM: [1] https://www.phytec.eu/en/produkte/development-kits/phyboard-nash/ [2] https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> Reviewed-by: Wadim Egorov <w.egorov@phytec.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: dts: imx8mp-var-som: Fix LDO5 shutdown causing SD card timeoutHimanshu Bhavani
Fix SD card timeout issue caused by LDO5 regulator getting disabled after boot. The kernel log shows LDO5 being disabled, which leads to a timeout on USDHC2: [ 33.760561] LDO5: disabling [ 81.119861] mmc1: Timeout waiting for hardware interrupt. To prevent this, set regulator-boot-on and regulator-always-on for LDO5. Also add the vqmmc regulator to properly support 1.8V/3.3V signaling for USDHC2 using a GPIO-controlled regulator. Fixes: 6c2a1f4f71258 ("arm64: dts: imx8mp-var-som-symphony: Add Variscite Symphony board and VAR-SOM-MX8MP SoM") Signed-off-by: Himanshu Bhavani <himanshu.bhavani@siliconsignals.io> Acked-by: Tarang Raval <tarang.raval@siliconsignals.io> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: defconfig: Add Toradex Embedded Controller configFrancesco Dolcini
Enable config for Toradex SMARC Embedded Controller, this is required for proper reset and power-off functionalities on Toradex SMARC iMX8M Plus. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: dts: freescale: imx8mp-toradex-smarc: use generic gpio node nameFrancesco Dolcini
Use generic node name for the SoM GPIO expander, following the Devicetree Specification generic node names recommendation. Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: dts: freescale: imx8mp-toradex-smarc: add gpio expanderEmanuele Ghidoli
Add gpio expander node to the device tree and the related nodes. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: dts: freescale: imx8mp-toradex-smarc: add embedded controllerEmanuele Ghidoli
Add the embedded controller node to the device tree, this is required for reset and power-off functionalities. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: dts: freescale: imx8mp-toradex-smarc: add fan PWM configurationFrancesco Dolcini
Configure correctly the FAN pwm output (inverted). Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: dts: imx93-tqma9352-mba91xxca: disable Open Drain for MDIOMarkus Niebel
Using the MDIO pins with Open Drain causes spec violations of the signals. Revert the changes. This is similar to commit 14e66e4b13221 ("Revert "arm64: dts: imx93-tqma9352-mba93xxca: enable Open Drain for MDIO"") Fixes: e5bc07026f94 ("arm64: add initial device tree for TQMa93xx/MBa91xxCA") Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: dt: imx95: Add TQMa95xxSAAlexander Stein
Add initial support for TQMa95xxSA module compatible to SMARC-2. There is a common device tree for all variants with e.g. reduced CPU count. It supports LPUART7 for console, CAN, PCIe I2C, SPI, USB3.0, USB2.0, Audio, SDHC1/2 and QSPI as storage. [1] https://www.tq-group.com/en/products/tq-embedded/arm-architecture/tqma95xxsa/ Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64/cpuinfo: only show one cpu's info in c_show()Ye Bin
Currently, when ARM64 displays CPU information, every call to c_show() assembles all CPU information. However, as the number of CPUs increases, this can lead to insufficient buffer space due to excessive assembly in a single call, causing repeated expansion and multiple calls to c_show(). To prevent this invalid c_show() call, only one CPU's information is assembled each time c_show() is called. Signed-off-by: Ye Bin <yebin10@huawei.com> Link: https://lore.kernel.org/r/20250421062947.4072855-1-yebin@huaweicloud.com Signed-off-by: Will Deacon <will@kernel.org>
2025-05-09arm64: dts: imx: Align wifi node name with bindingsKrzysztof Kozlowski
Since commit 3c3606793f7e ("dt-bindings: wireless: bcm4329-fmac: Use wireless-controller.yaml schema"), bindings expect 'wifi' as node name: imx8mm-var-som-symphony.dtb: bcrmf@1: $nodename:0: 'bcrmf@1' does not match '^wifi(@.*)?$' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: dts: freescale: add initial device tree for TQMa8XxSAlexander Stein
This adds support for TQMa8XQPS and TQMa8XDPS modules on MB-SMARC-2 board. As the only difference is the mounted SoC, both module and baseboard files are shared. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: dts: imx8mp-tqma8mpql-mba8mp-ras314: Add Raspberry Pi Camera V2 overlayAlexander Stein
This overlay configures IMX219 MIPI-CSI-2 camera attached to ISP1. Also add additional overlay both using LVDS display and camera. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: dts: imx8mp-tqma8mpql-mba8mp-ras314: Add LVDS device tree overlayMartin Schmiedel
This adds an overlay for the supported LVDS display tianma tm070jvhg33. The LVDS interface is the same as for MBa8MPxL so the already existing overlay can be reused on this platform. Signed-off-by: Martin Schmiedel <Martin.Schmiedel@tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: dts: freescale: Add minimal dts support for imx943 evkJacky Bai
Add the minimal board dts support for i.MX943 EVK. Only the console uart, SD & eMMC are enabled for linux basic boot. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64: dts: freescale: Add basic dtsi for imx943Jacky Bai
Add the minimal dtsi support for i.MX943. i.MX943 is the first SoC of i.MX94 Family, create a common dtsi for the whole i.MX94 family, and the specific dtsi part for i.MX943. The clock, power domain and perf index need to be used by the device nodes for resource reference, add them along with the dtsi support. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-05-09arm64/mm: Batch barriers when updating kernel mappingsRyan Roberts
Because the kernel can't tolerate page faults for kernel mappings, when setting a valid, kernel space pte (or pmd/pud/p4d/pgd), it emits a dsb(ishst) to ensure that the store to the pgtable is observed by the table walker immediately. Additionally it emits an isb() to ensure that any already speculatively determined invalid mapping fault gets canceled. We can improve the performance of vmalloc operations by batching these barriers until the end of a set of entry updates. arch_enter_lazy_mmu_mode() and arch_leave_lazy_mmu_mode() provide the required hooks. vmalloc improves by up to 30% as a result. Two new TIF_ flags are created; TIF_LAZY_MMU tells us if the task is in the lazy mode and can therefore defer any barriers until exit from the lazy mode. TIF_LAZY_MMU_PENDING is used to remember if any pte operation was performed while in the lazy mode that required barriers. Then when leaving lazy mode, if that flag is set, we emit the barriers. Since arch_enter_lazy_mmu_mode() and arch_leave_lazy_mmu_mode() are used for both user and kernel mappings, we need the second flag to avoid emitting barriers unnecessarily if only user mappings were updated. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Ryan Roberts <ryan.roberts@arm.com> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Tested-by: Luiz Capitulino <luizcap@redhat.com> Link: https://lore.kernel.org/r/20250422081822.1836315-12-ryan.roberts@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2025-05-09arm64/mm: Support huge pte-mapped pages in vmapRyan Roberts
Implement the required arch functions to enable use of contpte in the vmap when VM_ALLOW_HUGE_VMAP is specified. This speeds up vmap operations due to only having to issue a DSB and ISB per contpte block instead of per pte. But it also means that the TLB pressure reduces due to only needing a single TLB entry for the whole contpte block. Since vmap uses set_huge_pte_at() to set the contpte, that API is now used for kernel mappings for the first time. Although in the vmap case we never expect it to be called to modify a valid mapping so clear_flush() should never be called, it's still wise to make it robust for the kernel case, so amend the tlb flush function if the mm is for kernel space. Tested with vmalloc performance selftests: # kself/mm/test_vmalloc.sh \ run_test_mask=1 test_repeat_count=5 nr_pages=256 test_loop_count=100000 use_huge=1 Duration reduced from 1274243 usec to 1083553 usec on Apple M2 for 15% reduction in time taken. Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Ryan Roberts <ryan.roberts@arm.com> Tested-by: Luiz Capitulino <luizcap@redhat.com> Link: https://lore.kernel.org/r/20250422081822.1836315-10-ryan.roberts@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2025-05-09arm64/mm: Hoist barriers out of set_ptes_anysz() loopRyan Roberts
set_ptes_anysz() previously called __set_pte() for each PTE in the range, which would conditionally issue a DSB and ISB to make the new PTE value immediately visible to the table walker if the new PTE was valid and for kernel space. We can do better than this; let's hoist those barriers out of the loop so that they are only issued once at the end of the loop. We then reduce the cost by the number of PTEs in the range. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Ryan Roberts <ryan.roberts@arm.com> Tested-by: Luiz Capitulino <luizcap@redhat.com> Link: https://lore.kernel.org/r/20250422081822.1836315-7-ryan.roberts@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2025-05-09arm64: hugetlb: Use __set_ptes_anysz() and __ptep_get_and_clear_anysz()Ryan Roberts
Refactor the huge_pte helpers to use the new common __set_ptes_anysz() and __ptep_get_and_clear_anysz() APIs. This provides 2 benefits; First, when page_table_check=on, hugetlb is now properly/fully checked. Previously only the first page of a hugetlb folio was checked. Second, instead of having to call __set_ptes(nr=1) for each pte in a loop, the whole contiguous batch can now be set in one go, which enables some efficiencies and cleans up the code. One detail to note is that huge_ptep_clear_flush() was previously calling ptep_clear_flush() for a non-contiguous pte (i.e. a pud or pmd block mapping). This has a couple of disadvantages; first ptep_clear_flush() calls ptep_get_and_clear() which transparently handles contpte. Given we only call for non-contiguous ptes, it would be safe, but a waste of effort. It's preferable to go straight to the layer below. However, more problematic is that ptep_get_and_clear() is for PAGE_SIZE entries so it calls page_table_check_pte_clear() and would not clear the whole hugetlb folio. So let's stop special-casing the non-cont case and just rely on get_clear_contig_flush() to do the right thing for non-cont entries. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Ryan Roberts <ryan.roberts@arm.com> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Tested-by: Luiz Capitulino <luizcap@redhat.com> Link: https://lore.kernel.org/r/20250422081822.1836315-6-ryan.roberts@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2025-05-09arm64/mm: Refactor __set_ptes() and __ptep_get_and_clear()Ryan Roberts
Refactor __set_ptes(), set_pmd_at() and set_pud_at() so that they are all a thin wrapper around a new common __set_ptes_anysz(), which takes pgsize parameter. Additionally, refactor __ptep_get_and_clear() and pmdp_huge_get_and_clear() to use a new common __ptep_get_and_clear_anysz() which also takes a pgsize parameter. These changes will permit the huge_pte API to efficiently batch-set pgtable entries and take advantage of the future barrier optimizations. Additionally since the new *_anysz() helpers call the correct page_table_check_*_set() API based on pgsize, this means that huge_ptes will be able to get proper coverage. Currently the huge_pte API always uses the pte API which assumes an entry only covers a single page. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Ryan Roberts <ryan.roberts@arm.com> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Tested-by: Luiz Capitulino <luizcap@redhat.com> Link: https://lore.kernel.org/r/20250422081822.1836315-5-ryan.roberts@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2025-05-09arm64: hugetlb: Refine tlb maintenance scopeRyan Roberts
When operating on contiguous blocks of ptes (or pmds) for some hugetlb sizes, we must honour break-before-make requirements and clear down the block to invalid state in the pgtable then invalidate the relevant tlb entries before making the pgtable entries valid again. However, the tlb maintenance is currently always done assuming the worst case stride (PAGE_SIZE), last_level (false) and tlb_level (TLBI_TTL_UNKNOWN). We can do much better with the hinting; In reality, we know the stride from the huge_pte pgsize, we are always operating only on the last level, and we always know the tlb_level, again based on pgsize. So let's start providing these hints. Additionally, avoid tlb maintenace in set_huge_pte_at(). Break-before-make is only required if we are transitioning the contiguous pte block from valid -> valid. So let's elide the clear-and-flush ("break") if the pte range was previously invalid. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Ryan Roberts <ryan.roberts@arm.com> Tested-by: Luiz Capitulino <luizcap@redhat.com> Link: https://lore.kernel.org/r/20250422081822.1836315-3-ryan.roberts@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2025-05-09arm64: hugetlb: Cleanup huge_pte size discovery mechanismsRyan Roberts
Not all huge_pte helper APIs explicitly provide the size of the huge_pte. So the helpers have to depend on various methods to determine the size of the huge_pte. Some of these methods are dubious. Let's clean up the code to use preferred methods and retire the dubious ones. The options in order of preference: - If size is provided as parameter, use it together with num_contig_ptes(). This is explicit and works for both present and non-present ptes. - If vma is provided as a parameter, retrieve size via huge_page_size(hstate_vma(vma)) and use it together with num_contig_ptes(). This is explicit and works for both present and non-present ptes. - If the pte is present and contiguous, use find_num_contig() to walk the pgtable to find the level and infer the number of ptes from level. Only works for *present* ptes. - If the pte is present and not contiguous and you can infer from this that only 1 pte needs to be operated on. This is ok if you don't care about the absolute size, and just want to know the number of ptes. - NEVER rely on resolving the PFN of a present pte to a folio and getting the folio's size. This is fragile at best, because there is nothing to stop the core-mm from allocating a folio twice as big as the huge_pte then mapping it across 2 consecutive huge_ptes. Or just partially mapping it. Where we require that the pte is present, add warnings if not-present. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Ryan Roberts <ryan.roberts@arm.com> Tested-by: Luiz Capitulino <luizcap@redhat.com> Link: https://lore.kernel.org/r/20250422081822.1836315-2-ryan.roberts@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2025-05-09arm64: dts: ti: k3-j722s-evm: Add overlay for TEVI OV5640Vaishnav Achath
TechNexion TEVI OV5640 camera is a 5MP camera that can be used with J722S EVM through the 22-pin CSI-RX connector. Add a reference overlay for quad TEVI OV5640 modules on J722S EVM. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250509091911.2442934-5-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-09arm64: dts: ti: k3-j722s-evm: Add overlay for quad IMX219Vaishnav Achath
RPi v2 Camera (IMX219) is an 8MP camera that can be used with J722S EVM through the 22-pin CSI-RX connector. Add a reference overlay for quad IMX219 RPI camera v2 modules on J722S EVM Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250509091911.2442934-4-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-09arm64: dts: ti: j722s-evm: Add MUX to control CSI2RXYemike Abhilash Chandra
J722S EVM has the CSI2RX routed to a MIPI CSI connector and to 22-pin RPi camera connector through an analog mux with GPIO control, model mux so that an overlay can control the mux state according to connected cameras. Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250509091911.2442934-3-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-09arm64: dts: ti: j722s-evm: Add DT nodes for power regulatorsYemike Abhilash Chandra
Add device tree nodes for two regulators on the J722S-EVM. VSYS_3V3 is the output of LM5141-Q1, and it serves as an input to TPS22990 which produces VSYS_3V3_EXP [1]. VSYS_3V3_EXP serves as vin-supply to CSI RPI Connectors. Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> [1]: https://www.ti.com/lit/zip/sprr495 Link: https://lore.kernel.org/r/20250509091911.2442934-2-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-09arm64: dts: ti: k3-am62a-phycore-som: Reserve main_timer2 for C7x DSPDaniel Schultz
C7x DSP uses main_timer2, so mark it as reserved in linux DT. Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Reviewed-by: Judith Mendez <jm@ti.com> Link: https://lore.kernel.org/r/20250507070008.1231611-5-d.schultz@phytec.de Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-09arm64: dts: ti: k3-am62a-phycore-som: Reserve main_rti4 for C7x DSPDaniel Schultz
The main rti4 watchdog timer is used by the C7x DSP, so reserve the timer in the linux device tree. Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Reviewed-by: Judith Mendez <jm@ti.com> Link: https://lore.kernel.org/r/20250507070008.1231611-4-d.schultz@phytec.de Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-09arm64: dts: ti: k3-am62a-phycore-som: Enable Co-processorsDaniel Schultz
For every remote processor, set up dedicated memory regions and associate the required mailbox channels. Allocate two memory areas per remote core: one 1MB region for vring shared buffers, and another for external memory used by the remote processor for its resource table and trace buffer. Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Reviewed-by: Andrew Davis <afd@ti.com> Reviewed-by: Judith Mendez <jm@ti.com> Link: https://lore.kernel.org/r/20250507070008.1231611-3-d.schultz@phytec.de Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-09arm64: dts: ti: k3-am62-phycore-som: Enable Co-processorsDaniel Schultz
For every remote processor, set up dedicated memory regions and associate the required mailbox channels. Allocate two memory areas per remote core: one 1MB region for vring shared buffers, and another for external memory used by the remote processor for its resource table and trace buffer. Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Reviewed-by: Wadim Egorov <w.egorov@phytec.de> Reviewed-by: Andrew Davis <afd@ti.com> Reviewed-by: Judith Mendez <jm@ti.com> Link: https://lore.kernel.org/r/20250507070008.1231611-2-d.schultz@phytec.de Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-09arm64: dts: ti: k3-am62x-phyboard-lyra-gpio-fan: Update cooling mapsDaniel Schultz
Rename 'main0_thermal_trip0' to a more descriptive name that includes 'fan', as the current name is too generic for a fan control trip point. Move the fan to a new cooling map to avoid overwriting the passive trip point used for CPU frequency throttling when this overlay is enabled. Also, add the fan to the existing cooling map. Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Reviewed-by: Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20250506114134.3514899-2-d.schultz@phytec.de Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-09arm64: dts: ti: k3-am62a: Enable CPU freq throttling on thermal alertDaniel Schultz
Enable throttling down the CPU frequency when an alert temperature threshold (lower than the critical threshold) is reached. Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20250506114134.3514899-1-d.schultz@phytec.de Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-09arm64: dts: ti: k3-j721e-common-proc-board: Enable OSPI1 on J721EPrasanth Babu Mantena
J721E SoM has MT25QU512AB Serial NOR flash connected to OSPI1 controller. Enable ospi1 node in device tree. Fixes: 73676c480b72 ("arm64: dts: ti: k3-j721e: Enable OSPI nodes at the board level") Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com> Link: https://lore.kernel.org/r/20250507050701.3007209-1-p-mantena@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
generated by cgit (git 2.34.1) at 2025-07-19 07:28:15 +0000